# [SI-LIST] : Re: approximations for partial self inductance

From: Howard Johnson (howiej@sigcon.com)
Date: Wed Mar 14 2001 - 10:22:01 PST

Dear Itzhak Hirshtal and Brian Young,

The difficulties with approximating the inductance
of a via are even worse than you
may have suspected. Both approximations are flawed whether
you use +1 or -3/4, (or, as I have also seen, -1).

The issue of the exact constant (1, -3/4, or something
the path of returning signal current. (Current always
makes a loop; when signal current traverses the via,
a returning signal current flows SOMEWHERE in
the opposite direction.). It is a principle
of Maxwell's equations that high-speed returning signal
current will flow in whatever path produces the
least overall inductance.

Let's do an example involving a signal via that
dives down through a thick, multi-layer board.
If the signal in question changes reference
planes as it traverses the via,
then the returning signal current will also have to
change planes, meaning that the returning signal
current will flow through one or more vias (often
leading to bypass capacitors) as it moves from
plane to plane. For example, if the signal starts
out on the top layer, the returning signal current
is flowing on the nearest reference plane (call it
layer 2). If the via conducts the signal current
down to the bottom layer (16), then the returning
signal current at that point must be flowing on
the nearest (bottom-most) reference plane, call it 15.
Somehow the returning signal current has to hop from
reference plane 2 to reference plane 15 in the
vicinity of the via.

If you examine the space between the planes, the
magnetic fields within are created partly by
the signal current, and in equal measure (but in
differnt locations) by the returniing signal
current, which flows on different vias. The
total magnetic flux between the outgoing and
returning vias defines the inductance.
Specifically, to calculate the effective
inductance of via (A), you must first specify the
location of the return path, via (B), and then
calculate the total magnetic flux in the area
between the two vias. The total magnetic flux
generated by a signal current of one amp, in units
of webers, equals the inductance.
In the case of more complex return-path
configurations, other considerations apply.
I think at this point that the following
formulii for the effective series inductance
of a via are pretty good:

For a signal which pops from one side of the
plane, through a via, to the opposite side
of the same plane (i.e., the return current
doesn't have to jump planes), the via
inductance is very, very low. This is a best-case
scenario. I don't know a good way to make this
calculation except with a true 3-D E&M field solver.

For a signal which first uses reference-plane A,
and then changes (through a via) to use
reference-plane B, I'll do several examples. In
all cases the separation between reference planes
is H. (It doesn't matter if there are other
unused reference planes in the way, only the
spacing between the two reference planes A and B
matter).

If the return current is carried mainly on one nearby
via, where the spacing from signal via to return via
is S and the via diameter is D:

L = 5.08*H*(2*ln(2*S/D)) [1]

If the return current is carried mainly on two vias
equally spaced on either side of the signal via,
where the spacing from signal via to either return via
is S and the via diameter is D:

L = 5.08*H*(1.5*ln(2*S/D) + 0.5*ln(2)) [2]

If the return current is carried mainly on four vias
equally spaced in a square pattern on four sides
of the signal via, where the spacing from signal via
to any return via is S and the via diameter is D:

L = 5.08*H*(1.25*ln(2*S/D) + 0.25*ln(2)) [3]

If the return current is carried mainly on a
coaxial return path completely encircling the signal
via, where the spacing from signal via
to the return path is S and the via diameter is D:

L = 5.08*H*(ln(2*S/D)) [4]

The last formula I hope you will recognize as the
inductance of a short section of coaxial cable with
length H and outer diameter 2*S. I hope this
recognition will lend credence to the idea that
the position of the returning current path is
an important variable in the problem.

My earlier formula was a gross approximation which
ignored the position of the returning current path,
and omission which I greatly regret. It made the
crude assumption that the return path was approximately
coaxial and located at a distance S=5.43*H. As you
note, when the inductance really matters a
more accurate approximation is needed.

To obtain a result as low as 5.08*H*(ln(2*S/D)-1)
you would have to assume the return path were coaxial
and located at a ridiculously small separation of
S=.735*H, or that the return path were a single via
located at some even closer distance.

On my web site http://signalintegrity.com under "articles"
there is a write-up about calculating the inductance of
a bypass capacitor that includes the above formulas for
vias, as well as some handy ways to estimate the
inductance of the capacitor body.

By the way, if you find a flaw in THIS write-up,

Best regards,
Dr. Howard Johnson

>>On the two versions of the equation, it looks to me like the version
>>in Johnson's book has a typo. When d>>r, the external partial
>>self-inductance of a straight round wire is
>>
>>L=5.08d*{ln(2d/r)-1}nH,
>>
>>where d is the length in inches, and r is the radius in inches.
>>The external inductance is a good approximation at high frequencies
>>where the skin effect shields the internal metal of the wire. At
>>low frequencies, the internal self-inductance needs to be
>>added to the external partial self-inductance to obtain
>>
>>L=5.08d*{ln(2d/r)-3/4}nH,
>>
>>which is the formula from Gover, as Eric pointed out.
>>
>>It seems that Johnson's book has the first (high-frequency) version
>>with a sign error on the 1 because he has
>>
>>L=5.08h*{ln(4h/d)+1}nH,
>>
>>where h is the length in inches, and d is the diameter in inches.
>>
>>
>>This formula should not be used for vias because it assumes that
>>the length is much greater than the diameter. To compute partial
>>self-inductance for vias, you should use the more complex formula
>>that does not have this assumption built in. The correct formula
>>is (5.49) from my book. This is the external partial self-inductance,
>>so if you want the low frequency inductance, you need to add the
>>internal inductance from (5.45).
>>
>>Finally, Grover does not actually derive much in his book. If you
>>are interested, the round wire formula above and many others are
>>derived in my book.
>>
>>Regards,
>>Brian Young
>>
>>
>>Eric Bogatin wrote:
>>>
>>> Itzhak-
>>>
>>> for the partial self inductance of a via that were given by
>>> myself and Howard Johnson. I wanted to provide some
>>> clarification. You wrote:
>>>
>>> (4) While calculating vias inductance, I've encountered 2 similar
>>> but
>>> different equations for this parameter. One is given by Mr. H.
>>> Johnson
>>> in his famous book (page 259), as follows:
>>>
>>> L=5d*{ln(2d/r)+1}nH.
>>>
>>> The other is given by Mr. Bogatin in one of his articles, and is:
>>>
>>> L=5d*{ln(2d/r)-3/4}nH.
>>>
>>> Can somwone explain the reason for the difference, or who is
>>> right? The
>>> difference starts to be quite critical when dealing with u-Vias!
>>>
>>> The approximation is for the partial self inductance of a round,
>>> solid rod, of radius, r and length d. The length is in units of
>>> inches, while the inductance is in units of nH.
>>>
>>> This is the approximation that was originally derived by Fred
>>> Grover, in his classic book, Inductance Calculations", in 1946. I
>>> just re-checked the one I offered, and it is correctly reproduced
>>> above. It is listed on page 35, eq 7, of his book. I think it has
>>> since been reprinted as a Dover Book.
>>>
>>> Keep in mind two things when using this approximation: 1st, it is
>>> an approximation. Grover says it is good to about 2%. I have
>>> found good agreement to better than 5% for wire bond structures.
>>> Approximations are wonderful tools to assist you in exploring
>>> design space, run in a spread sheet and play what-if trade offs.
>>> They give you good answers and let you see the geometry and
>>> materials trade offs. However, they are APPROXIMATIONS. You
>>> should never use an approximation in a situation where the
>>> accuracy of the answer may cost you significant time and expense.
>>> You should be using a 3D field solver that you have confidence
>>> in. One of the second order effects in this approximation, for
>>> example, is that it includes the "internal" self inductance. As
>>> the skin depth gets to be comparable to the geometrical cross
>>> section, the partial self inductance will decrease and reach a
>>> constant value when all the current is in the outer surface.
>>>
>>> The second thing to keep in mind when using this approximation is
>>> that it is for the PARTIAL self inductance of the via, under the
>>> assumptions of uniform current flow down the long axis. If you
>>> are using it in a situation where the length of the structure is
>>> comparable to the diameter, ie, d ~ 2r, the current distribution
>>> through the structure may not be even close to parallel to the
>>> long axis. Further, the actual loop inductance, which is what
>>> matters in a real circuit, is probably dominated by other
>>> elements than this small, squat element. The partial self
>>> inductance may depend strongly on the proximity of other
>>> conductors and how it affects the current flow through this via.
>>> If you are in a regime where worrying about the presence of the
>>> -3/4 term is important, you probably want to use a 3D field
>>> solver before any design signoff. A good 3D solver will calculate
>>> the actual current distribution through the via structure and the
>>> rest of the current path.
>>>
>>> I hope this helps.
>>>
>>> If anyone is interested, I have various application notes related
>>> to approximations to inductance and general principles related to
>>> inductance posted on our web page. These are listed as app notes
>>> with index numbers: 33, 32, 29, 25, and 9. You can find them
>>> under application notes at www.gigatest.com
>>>
>>> As always, comments are welcome.
>>>
>>> --eric
>>>
>>> From: Itzhak Hirshtal [mailto:hirshtal@is.elta.co.il]
>>> Sent: Monday, March 12, 2001 09:33
>>> To: si-list
>>> Subject: [SI-LIST] : Inductance and Decoupling
>>>
>>> Hello, all
>>>
>>> I've recently started to calculate the de-coupling needed for
>>> efficiently supplying the spike currents needed by high-speed
>>> devices.
>>> During this task, I've encountered several ambiguities and
>>> results that
>>> I would like to share with you and perhaps hear some (useful)
>>> feedback
>>> from you.
>>>
>>> (1) I tried to evaluate the situation for one high-pin-count
>>> device with
>>> several buses connected to it (essentially a bus bridge). Even
>>> calculating for just one synchronous bus (with 144 bits overall)
>>> I
>>> arrived to the result that a few Amps (maybe even 5) are drawn
>>> when all
>>> or most of this bus bits change state. I wonder what will be the
>>> result
>>> if I would calculate for an additional bus (assuming it's
>>> synchronous
>>> with the first). And what about the internal changes? They might
>>> be
>>> contributing even more than the external bus! (e.g., the Motorola
>>> PowerPC HW manual states that 90% of the power consumption of
>>> this
>>> device is drawn internally, not externally).
>>>
>>> (2) I've also tried to calculate the inductance of the decoupling
>>> capacitors connections to the device. Even assuming a 40-mil wide
>>> 50-mil
>>> long trace right above a reference plane for the connection I
>>> have app.
>>> L=150-200pH. If I can't connect at least one of the capacitor
>>> short I might have to do a direct connection via to a reference
>>> plane. I
>>> calculated this to have more than L=1nH!
>>>
>>> (3) I assumed the calculated peak currents change at a rate
>>> equivalent
>>> to the rise time of the device's output buffers. I don't know if
>>> it's
>>> true, but this seems to me the most logical thing to do. Even if
>>> I take
>>> it to be 2ns (1 ns is closer to worst-case, I believe), I get
>>> the
>>> result that I need 40 to 50 low-ESL decoupling capacitors for the
>>> case
>>> where L=1nH. Only if I succeed to connect the capacitors directly
>>> and
>>> close enough to both GND and VDD pins (L=150-200pH) do I get the
>>> result
>>> that it is sufficient to use 4-6 decoupling capacitors.
>>>
>>> (4) While calculating vias inductance, I've encountered 2 similar
>>> but
>>> different equations for this parameter. One is given by Mr. H.
>>> Johnson
>>> in his famous book (page 259), as follows:
>>>
>>> L=5d*{ln(2d/r)+1}nH.
>>>
>>> The other is given by Mr. Bogatin in one of his articles, and is:
>>>
>>> L=5d*{ln(2d/r)-3/4}nH.
>>>
>>> Can somwone explain the reason for the difference, or who is
>>> right? The
>>> difference starts to be quite critical when dealing with u-Vias!
>>>
>>> Thanks for anyone who makes the effort to read this email.
>>
>>
>>--
>>***************************************************************
>>* Brian Young phone: (512) 996-6099 *
>>* Somerset Design Center fax: (512) 996-7434 *
>>* Motorola, Austin, TX brian.young@motorola.com *
>>***************************************************************
>>
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>>
>_________________________________________________
>Dr. Howard Johnson
>tel 425.556.0800 fax 425.881.6149
>Signal Consulting, Inc.
>16541 Redmond Way #264
>Redmond, WA 98052
>http://signalintegrity.com -- High-Speed Digital Design
>books, tools, and workshops
>

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