Figure 7

3.1.3. Pattern framing

Continuous mode:

Supports voice super frame framing, LC Header, PI Header or PI Header mode.
Into the super frame and join the LC Terminator;
Support data 4.8kbps framing, add data LC Header, data and LC Terminator;
Support data 9.6kbps framing, add data LC Header, data and LC Terminator.

Time slot mode:

Supports voice super frame framing, LC Header, PI Header or PI Header mode.
Into the super frame and join the LC Terminator;
Supports 4.8kbps framing of various data types, adds data LC Header, data and LC Terminator;

3.2 How to use

Figure 8

• Voice LC Header:
  CPU 0x50 set to send the type 0x10, write 72bit LC data, write to send enable, the chip done CRC,
  BPTC, interleaved and framed in the next time slot to send, chip open voice coding, you can control the CPU to open voice coding.
  Receiving, on the other hand, gives the DataType, CC, PI, and 72bit LC data (or CRC check error) in the receive interrupt error).
  
• Voice PI Header:
  CPU 0x50 set to send type 0x00, write 80bit data, write to send enable, the chip done Header CRC,
  BPTC, interleaved and framed in the next slot.
  DataType, CC, PI and 80bit data (or CRC parity errors) are given in the receive interrupt.
  
• ? Voice super-frame (the actual operation, the use of A ~ F can be controlled separately):
  Before the voice superframe, the LC 72bit must be configured to generate the EMB in the superframe, identify and record the chip to (A ~ F) interrupt,
  gives the corresponding CC, PI and LCSS, the chip from the inside of the (Which may also be encoded by the CPU),
  and the framing is transmitted in the next time slot.
  (phew..)
  After receiving the LC information from the superframe, CC, PI, and LC are provided to the CPU, and the voice data can be transmitted through the RAM Sent to the CPU, you can also directly into the decoder's RAM in the received A frame, automatic (or CPU control) is turned on Speech decoding.
  A to F of the voice superframe are set from 0x50 to 0x18 to 0x68
  
• Voice LC Terminate:
  The CPU sets the send type 0x20 at 0x50 (Can not write 72bit data), Write to send enable,
  the chip done CRC, BPTC, interleaved and framed in the next slot to send.
  DataType, CC, PI and 72bit LC data (or CRC parity error) are given in the receive interrupt and are disabled Speech decoding (can be controlled by CPU off).
  DLL state mechanism in the loss of lock state, it will turn off speech decoding (CPU control can be closed), the chip Out of lock exception (interrupt).
  
• CSBK (80bit):
  CPU 0x50 set to send type 0x30, write 80bit data, write to send enable, the chip done CRC, BPTC, Interleaved and framed in the next slot to send. DataType, CC, PI and 80bit data (or CRC parity errors) are given in the receive interrupt.
• MBC Header:
  CPU 0x50 set to send type 0x40, write 80bit data, write to send enable, the chip done CRC, BPTC, Interleaved and framed in the next slot to send. DataType, CC, PI and 80bit data (or CRC parity errors) are given in the receive interrupt.
• MBC Intermediate / MBC Last (96bit):
  CPU 0x50 set to send type 0x50, write 96bit data, write to send enable, the chip done BPTC, Interleaved and framed in the next slot to send. DataType, CC, PI and 96bit data are given in the receive interrupt.
• Data Header (80bit):
  CPU 0x50 set to send type 0x60, write 80bit data, write to send enable, the chip done CRC, BPTC, Interleaved and framed in the next slot to send.
  DataType, CC, PI and 80bit data (or CRC parity errors) are given in the receive interrupt.
  Data Block (96/144 / 192bit requires packet data block SN, 9bit CRC and Fragment CRC): CPU in 0x50 set send type 0x70 / 0x80 / 0xA0, write 96/144/196bit data, write to send to enable, Chip done BPTC / Viterbi / no, interleaved and framed in the next time slot to send. DataType, CC, PI and 96bit data are given in the receive interrupt.
• Custom Frames:
  CPU 0x50 set to send the type 0xB0 ~ 0xF0, write 96bit data, write to send enable, the chip done BPTC, Interleaved and framed in the next slot to send.
  DataType, CC, PI and 96bit data are given in the receive interrupt.
  Note: If the SlotType field is not validated, it will be listed as invalid data, lost, but the chip will tell Layer is missing.
  

4 Call control layer mode

4.1 Protocol support

CSBK is used to activate the BS

This process is automatically processed when the MS initiates a relay call.

Supports FNS

Feature Not Supported signaling, using Response CSBK, set the corresponding value for feedback.

Group Call

Support the use of LC to determine the way FID and FLCO framing, CCL design time slot in line with the standard Of the group call state flow, matching time slot PTT event, the channel to apply for transmission rejection, channel transmission acceptance, voice access Delayed Access Voice Receiving, PTT Release, Voice End LC Transmission, Received Idle Voice End, Non-Active Receive voice exit termination and no signal reception termination.

Individual Call

Support direct call and OACSU call; Supports CSBK establishment and CSBK feedback signal control flow of OACSU call, supports abnormal feedback signal deal with;

Unaddress voice call

Support for addressless call mode address recognition, flow control;

All call

Support for the address of all call-way recognition, process control;

Broadcast (broadcast voice call)

Support broadcast address of the call mode, process control;

Open channel call (open voice channel call)

Support Group Call and Individual Call under the OVCM mode to call and receive calls; Using the provisions of the ETSI TS 102 361-2 standard LC, PDU control word requirements, and in strict accordance with the process design, time parameters can be set, using the provisions of the agreement Polite strategy;

Data information services

Unconfirmed data transmission

4.2 Instructions for use (Call Control Layer)

5. FM compatible (Frequency modulator and demodulator ?)

Figure 9

6. System Clock

Figure 10

[0x0b] = 0x28 = PLLM ( PLL Multiplier )

[0x0c] = 0x33 = 0b0011 0011
                  |||| \\\\_ PLL input divider,  PLLN  = 3
                  ||\\______ PLL output divider, PLLDO = 3
                  |\________ PLL 'not sleeping'
                  \_________ PLL 'in use' (not bypassed)

XTAL := 29.4912MHz  =: 2.94912e+07
PLLM := 0x28
PLLN := 3
PLLDO:= 3
CLK  := XTAL * PLLM / PLLN / (2*PLLDO)  =: 6.5536e+07

CLK := XTAL * PLLM / (PLLN+1) / (2*PLLDO) =: 4.9152e+07 = 49.152 MHz, q.e.d.

7. Interrupt Processing

• two transmit and receive handoff interrupts,
• a 30ms clock interrupt,
• and a system interrupt.

Figure 11 : C5000 RX and TX interrupts

Figure 11 b : C5000 'Time Slot' interrupt

1. Send request rejected
   This interrupt has no sub-status register, indicating that the transmit request was rejected because the channel was busy.
   
   
2. "The transmission starts"
   Start with the sub-state register 0x84, 0x85 can be masked by the corresponding interrupt Sub-shape(?).
   The status register indicates the seven types of interrupts that generate the start of transmission, including:
   
   • Voice delivery
   • The OACSU request is sent for the first time
   • The OACSU request is sent a second time
   • The Vocoder configuration returns an interrupt when the AMBE3000 is configured to use the CPU.
     (HR_C5000 to the CPU to send back the configuration complete interrupt)
   • Data is sent
   • Partial retransmission of data
   • All data retransmissions
   
   
3. "The transmission ends"
   Send the end of a sub-state register 0x86, the corresponding interrupt can be masked by 0x87 Sub-shape(?).
   State registers indicate the six kinds of interrupt generated to send end, including:
   
   • The voice ends normally
   • End of voice exception (transmission timeout)
   • Voice OACSU waits for a timeout
   • The data ends normally
   • Data abend (transmission timeout)
   • The data validation wait time-out
   
   
4. "After access"
   After the access interrupt has no sub-status register, after receiving the interrupt, indicating that the access voice communication is 'After the access mode'.
   
   
5. "Receive Data"
   The receive data interrupt has no sub-status register, but its receive data is received by register 0x51, using the DLLRecvDataType, DLLRecvCRC description of the received data type and the Wrong circumstances, CPU accordingly corresponding status display, you can also shield (? acknowledge or disable ?) the corresponding interrupt.
   
   
6. "Receive information"
   The receive information interrupt has the sub-state register 0x90, the sub-status register has only one type, 0 indicates the whole One message reception check is passed, and 1 indicates the entire message reception check error.
   
   
7. Abnormal exit
   Abnormal Exit Interrupts There are no sub-state registers, and the cause of the exception is an unintended internal state machine Interruption.
   
   
8. The physical layer operates independently to receive interrupts
   Physical Layer Separate Operation Reception Interrupts: There are no sub-state registers that are generated at the physical layer in a separate operating mode.
   

Figure 12 : System Interrupt Handler.
Branch by the bits read from register 0x82 ?

8. Data read and write

Figure 13 : SPI command transfer sequence

   Table 7

• 000 indicates operating state control Ram,
• 001 indicates that the operation of ancillary parameters configuration table,
• 010 denotes operation information data
• 011 denotes Operation tone
• 100 for the CMX638 Parameter configuration
• 101 represents a pair AMBE3000 parameter configuration

   Table 8

   Table 9

   Table 11

Figure 14

   Table 12

MUX0 is controlled by [0x06] [7: 6].

where [0x06] [7: 6] cannot be equal to 2'b11,
ie CMX638 and AMBE3000 cannot be open at the same time.
(when forcedly set to 2'b11, the effect is the same as 2'b00)

MUX1 is controlled by [0x06] [5].

when = 0, MUX0 → MUX1 → SendRam0,
when = 1, SPI1_In → MUX1 → SendRam0.

MUX2 is controlled by [0x06] [4].

when = 0, DMRRecv → MUX2 → RecvRam1;
when = 1, SendRam0 → MUX2 → RecvRam1, said custom sound.

MUX3 is controlled by [0x06] [3].

when = 0, RecvRam0 → MUX3 → SPI1_Out, that's protocol layer recording,
when = 1, SendRam1 → MUX3 → SPI1_Out, that's vocoder recording.

MUX4 is controlled by [0x06] [2: 1] and [0x10] [7],

  where [0x06] [1] has the highest priority, followed by [0x10] [7].
When [0x06] [1] = 1, it means to power on, incoming call,
    SPI2 → MUX4 → InCodec / ExCodec.
When [0x06] [1] = 0, [0x10] [7] = 1, Codec → MUX4 → FM
    and FM → MUX4 → Codec
When [0x06] [1] = 0, [0x10] [7] = 0,
    Codec → MUX4 → Vocoder and Vocoder → MUX4 → Codec.

9. Vocoder peripheral instructions

Figure 15

10. External Codec clock

 [0x30]=0x00     [0x31]=0x17     [0x32]=0x02     [0x33]=0xff
 (Mclk/BCLK,hi)  (Mclk/BCLK,lo)  (Mclk/LRCK,hi)  (Mclk/LRLK,lo)