From: Michael Nudelman ([email protected])
Date: Mon Feb 12 2001 - 06:16:23 PST
Perry:
Copper pads taken alone should not affect one wire. Right? As long as you do
not connect any coupled conductor with the common of a schematic (thus, no
return current flows in the coupled conductor (copper pad for that matter))
it is pretty much inactive and does not load the signal (we do not look into
second-order parasitics for now).
What it does, when you introduce a GND plane under a conductor, it will
create extra capacitance between the wire and the GND plane, lowering the
impedance. You can consider them even-paced capacitive loads, and you will
probably see this one long continuous capacitive bleep. May be rather small.
Same as if you just connected caps at the same pace between the wire and the
GND plane.
-----Original Message-----
From: Perry Qu [mailto:[email protected]]
Sent: Monday, February 12, 2001 08:51
To: Ritchey Lee
Cc: DORIN OPREA; SI-LIST
Subject: Re: [SI-LIST] : Copper balance
Hi! Richey:
Thank you for your comments. I did some simulation recently using a 3D field
solver to calculate how the isolated copper dots affect the transmission
line. My original intention is not to study the copper dots due to copper
balance, but to study how embedded microstrip lines are affected by copper
pads on the components side. e.g., I saw many routing done in a way similar
to the cases shown in the attached jpg file, where you have repeated copper
pads right on top of a embeded-microstrip line.
From the simulation, I find that the copper dots will increase the
capacitance of the transmission line while the inductance does not change
much. This results in lower impedance as you mentioned in your comments. In
my particular simulation, the impedance is about 6% lower for transmission
line with copper dots.
Regards
Perry Qu
Ritchey Lee wrote:
> These bits of copper don't function as antennas. If there are many of
> them close to controlled impedance traces, they will lower the
> impedance. That's the primary concern. It is pretty easy to simulate
> their effect with a 2D field solver. That's much better than some
> arbitrary "20H" or other rule. What one does is analyse how near copper
> in the same layer or adjacent layers lower impedance. Then, it is a
> matter of moving the copper away and seeing when the effect on impedance
> is tolerable.
>
> What one learns when this is done is that this kind of fill on an
> adjacent layer when it lies over the top of a trace has a noticable
> effect on impedance. When this fill is on the same layer, it has no
> more effect than adjacent traces. So, on same layer, the spacing that
> is acceptable for near traces works. On adjacent layers, no copper over
> a trace and back away the same spacing as for adjacent layer.
>
> Hope this helps.
>
> Lee
>
> Dave Hoover wrote:
>
> > Dorin,
> > (From a Fabrication Stand Point)
> > My experience is more around something I've heard
> > called the "antennae effect" where the floating
> > (isolated) copper will be capacitive and couple with
> > any signals close by. So many fabricators tend to
> > break the copper thieving up into small isolated
> > features. (circles or squares) A couple of important
> > things to comment on would be to maintain the
> > isolation of these features away from other traces or
> > pads. (20H Rule) And to make sure that when the
> > fabricator generates the thieving that they also
> > include ALL signals contained within each reference
> > plane group. (i.e., a dualstripline would need both
> > signals (temporarily) merged to generate the pattern.
> > Or if layers 1 and two were signals, they would also
> > need to be merged to generate the thieving or else the
> > squares might end up being rignt on top of a signal
> > trace.)
> >
> > Dave Hoover - Director of Technology
> >
> > --- DORIN OPREA <[email protected]> wrote:
> > > Thanks Chris. The main problem is the PCB vendor
> > > wanted to have 40% copper
> > > convereage on the layer and this implies small
> > > spacing between the floating copper
> > > geometries. Having squares 5x5 mm with the spacing
> > > 10 mm will give < 25% copper
> > > coverage; therefore less spacing is required. But
> > > what is the smallest spacing and
> > > what is the copper geometry to get 40% ?
> > >
> > > Dorin
> > >
> > >
> > >
> > > Chris Padilla wrote:
> > >
> > > > It is called thieving and I've found so signifcant
> > > EMI results positive or
> > > > negative as a result. Just set a spacing criteria
> > > from any components like
> > > > "no closer than 500 mils to any componenet or
> > > trace or via or whatever."
> > > >
> > > > If the board has lots of blank space to fill, the
> > > EMI team may wish to
> > > > consider making embedded caps with the free space
> > > and copper flood
> > > > depending on the reference plane nearby. I have
> > > found these caps to be of
> > > > significant importance in controlling emissions
> > > and they are basically "free!"
> > > >
> > > > Good Luck----->Chris
> > > >
> > > > >Hi,
> > > > >
> > > > >I am working now on the copper balance issue we
> > > have on our PCBs. On the
> > > > >outer layer beneath the converter a copper
> > > surface is required (E
> > > > >shielding) which generates the copper balance
> > > issue on that particular
> > > > >layer and also throughout the stack up. Thus, the
> > > unpopulated copper
> > > > >space is filled with square or circle floating
> > > copper surfaces separated
> > > > >in-between. These squares are overlapping
> > > throughout the stack up. The
> > > > >question: what is the best copper geometry, its
> > > dimension and the
> > > > >spacing between these geometries ?. Copper
> > > balance requires as much
> > > > >copper as possible but EMC wants no floating
> > > copper and very weak
> > > > >coupling between noisy areas such as converter
> > > and any functional
> > > > >digital area.
> > > > >
> > > > >Your help is really appreciated,
> > > > >Dorin
> > > > >
> > > > >
> > > > >**** To unsubscribe from si-list or
> > > si-list-digest: send e-mail to
> > > > >[email protected]. In the BODY of
> > > message put: UNSUBSCRIBE
> > > > >si-list or UNSUBSCRIBE si-list-digest, for more
> > > help, put HELP.
> > > > >si-list archives are accessible at
> > > http://www.qsl.net/wb6tpu
> > > > >****
> > >
> > >
> > > **** To unsubscribe from si-list or si-list-digest:
> > > send e-mail to
> > > [email protected]. In the BODY of message
> > > put: UNSUBSCRIBE
> > > si-list or UNSUBSCRIBE si-list-digest, for more
> > > help, put HELP.
> > > si-list archives are accessible at
> > > http://www.qsl.net/wb6tpu
> > > ****
> > >
> >
> > __________________________________________________
> > Do You Yahoo!?
> > Get personalized email addresses from Yahoo! Mail - only $35
> > a year! http://personal.mail.yahoo.com/
> >
> > **** To unsubscribe from si-list or si-list-digest: send e-mail to
> > [email protected]. In the BODY of message put: UNSUBSCRIBE
> > si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
> > si-list archives are accessible at http://www.qsl.net/wb6tpu
> > ****
>
> **** To unsubscribe from si-list or si-list-digest: send e-mail to
> [email protected]. In the BODY of message put: UNSUBSCRIBE
> si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
> si-list archives are accessible at http://www.qsl.net/wb6tpu
> ****
**** To unsubscribe from si-list or si-list-digest: send e-mail to
[email protected]. In the BODY of message put: UNSUBSCRIBE
si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu
****
This archive was generated by hypermail 2b29 : Tue May 08 2001 - 14:30:49 PDT