[SI-LIST] : Simple load question

About this list Date view Thread view Subject view Author view

From: [email protected]
Date: Wed Jan 24 2001 - 14:58:19 PST

One of our engineers is very concerned about the "maximum capacitive load"
specification on a processor he's using. This is a relatively fast part with
rise and fall times on the order of 600 psec. The loads are distributed across
several memory devices, anywhere from 1 to 9 inches away. Am I correct in
thinking that if the driver sees only the capacitive component of the
transmission line impedance initially and then the "reflected capacitance" of
each input one round trip reflection time later?


Brent DeWitt

******************** CONFIDENTIALITY NOTICE ********************
This notice has been automatically added to all Datex-Ohmeda Internet messages.

This E-mail communication may contain information that is confidential and
privileged. The information is intended to be for the use of the addressee
only. If you are not the addressee, please note that any disclosure, copy,
distribution or use of the contents of this message is prohibited.

**** To unsubscribe from si-list or si-list-digest: send e-mail to
[email protected] In the BODY of message put: UNSUBSCRIBE
si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu

About this list Date view Thread view Subject view Author view

This archive was generated by hypermail 2b29 : Tue May 08 2001 - 14:30:43 PDT