From: Doug Hopperstad ([email protected])
Date: Tue Jan 23 2001 - 11:35:31 PST
Javin,
The +/- differential pair spacing should be kept to a minimum for
common-mode coupling. The actual spacing will depend on your board stackup
and dielectric material. For a reference, a dual-stripline using FR408 would
yield the following:
---------------- Ground plane
--(1+)-- --(1-)-- Trace layer: differential pair
--(2+)-- --(2-)-- Trace layer: Orthogonal routing to the upper trace
layer.
---------------- Ground plane
The dielectric spacing between the plane and trace layer = 4 mils
The trace-to-trace layer spacing = 14 mils
The trace width = 5 mils (1w)
The trace-to-trace spacing = (1+) to (1-) = 10 mils edge-to-edge
The above configuration will yield a 99.54 ohm differential impedance.
With regard to the second question: I try to keep the trace lengths matched
as close as possible. At the pins, the pinout should be setup such that the
+/- pins are next to each other to avoid a routing mismatches.
Doug Hopperstad
Qlogic
-----Original Message-----
From: Javin Olson [mailto:[email protected]]
Sent: Tuesday, January 23, 2001 10:15 AM
To: [email protected]
Subject: [SI-LIST] : diff pair routing rules
All,
I have a couple of general SI/routing rules I would like to get
information on,
and thought this may be the forum to do so.
1. What is the general rule of trace to trace spacing of a differential
pair signals (positive trace to negative trace, NOT pair to pair
spacing)?
PECL and LVDS, are different spacings recommended?
2. When routing a differential pair to pins that are a few rows apart,
is it best to keep the diff. pairs close as long as possible and then
route straight to the pin; or should the net that is shorter be
(mini) wrapped so that the diff pair lengths are exactly matched? What
is
more important, keeping the diff pair nets routed togother, or breaking
off the short route near the end of the trace to wrap it and make it as
long as the long route net?
Any thoughts?
Thanks you for your comments.
Javin Olson
Plexus Technology Group
Digital Design Engineer
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