From: Ajit Madhekar ([email protected])
Date: Mon Jan 22 2001 - 23:33:59 PST
> Looking for a rule of thumb for the number of power pads for a chip
running
> 135Mhz, 32Bits, driving at slopes of 1nSec to 3.3V 25pf.
I am not sure how did you get the figure about driving of the load of 25 pf
in 1 ns.
What PADS ( driving capacity in mA) you have used ?
Now about the question
Depends,
Generally , as a rule of thumb we follow one VDD VSS pair after each 4-5
functional pins.
Again VDD and VSS for IO as well as CORE are to be distributed.
It also depends on the power consuption of a chip.
But the ideal procedure can be
Get the power report from synopsys .saif files by including the PLIs in
simulations. This will give you the core power
Add the IO power + memory/other blocks power that will give you total power
of chip.
( I assume the design is pure digital.)
Now depending on that result decide the number of PADS.
I hope I am clear
Regards,
Ajit Madhekar
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