From: Haller, Robert ([email protected])
Date: Sat Jan 20 2001 - 09:35:18 PST
Ken, and Tony,
I'll try and address the test circuit versus actual circuit.
Many have already brought up the fact that the delta between
driving the "Standard load" and the "Actual Load" is the Wire Prop
delay you feed into your static timing verifier (or use for manual
'back of the envelope calculation'). This is similar to the
'slope-intercept' technique that is often documented in databooks.
The issue often missed is that this works fine if the IF
the I/O cell drive characteristics are linear versus capacitance.
You can create plot of Capacitance versus Prop delay. If it is a straight
line then it doesn't really matter what value you pick to specify the
standard load. If it is NOT a straight line and the standard load is
NOT equal to your actual load then a Timing error is introduced.
If the CHIP manufacturer (and some do this) specifies a standard
load that is VERY SIMILAR to the actual load (Look at how
HIGH SPEED RAMS are specified) the error will be small or zero.
As timing margins shrink it becomes more important to understand
these approximations and eliminate them if possible. If you
run an 'end-to-end' spice simulation you can eliminate that
approximation/error .
As DC Sessions use to say; we need to eliminate the 50 Pf
standard load drawn in the ancient caves.
Regards,
Bob Haller
Cereva Networks
[email protected]
508-787-5365
P.S. to Todd's original question - We use both IBIS and HSPICE
each as benefits. For verification strategies read Greg and my
Designcon98 paper. Remember SPICE is a behavioral simulator too,
usually one level closer to the undelying physics.
-----Original Message-----
From: Ken Wu [mailto:[email protected]]
Sent: Friday, January 19, 2001 4:36 PM
To: 'Dunbar, Tony'; '[email protected]'
Subject: RE: [SI-LIST] : IBIS vs HSpice
Tony,
Thanks for the reply.
My understanding is that IBIS model uses the test-circuit(Vref, Cref and
Rref) to
derive the rising/falling waveforms and flight time of IO. SI tool vendors
then
apply the rising/falling waveforms (and probably flight time) to real load
to figure
out the IO delay(flight time). My question is how accurate it's going to be
since
the rising/falling waveforms are based on test-circuit instead of real load.
Also, what do you mean the real circuit delay should have the test-load
result substracted?
Can you be a little bit more detail on this?
Regards,
Ken
-----Original Message-----
From: Dunbar, Tony [mailto:[email protected]]
Sent: Friday, January 19, 2001 12:43 PM
To: '[email protected]'
Subject: RE: [SI-LIST] : IBIS vs HSpice
Ken,
Just a slight correction or clarification, if I may: The IO delay of the
buffer model can be considered to be "provided" in a Quad model by way of
the time-to-VM parameter. In an IBIS model - a complete one, at least - the
related parameters are the test-circuit (Vref, Cref, Rref) and the Vmeas
parameter. These do not provide the IO delay, per se. Instead, they provide
for a capable IBIS simulator to use these to do a simulation to derive the
delay. Typically, the delay is reported as the time it takes the so-called
test waveform to cross the Vmeas level. This is the simulation equivalent
(or re-creation) of what the silicon vendor has done in order to provide the
delay numbers in the datasheet. Then, the IBIS simulator does the "real"
interconnect circuit simulation that, as you point out, is typically very
different from the test-load simulation - just as it is very different than
what the Si manufacturer did to also report his numbers. The actual real
circuit delay should then have the test-load result subtracted to obtain the
true loaded flight time.
I'll leave it to others to comment on the accuracy angle. I'm from one of
those SI tools vendor companies and I will be horribly hissed and booed if I
encroach into that domain!
Regards,
Tony
-----Original Message-----
From: Ken Wu [mailto:[email protected]]
Sent: Friday, January 19, 2001 1:00 PM
To: [email protected]
Subject: [SI-LIST] : IBIS vs HSpice
Talking about IBIS vs HSpice, I want to post one of my concerns: how
accurate it is using IBIS model to
do IO timing analysis? Typically in IBIS model the IO delay is provided with
test load while in really the
real load could be quite different from test load. With spice model, the IO
delay can be easily figured out
through spice simulation while with IBIS model, I don't know how accurate it
is when performing IO delay
analysis. Any thought on this?
Ken Z. Wu
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