From: [email protected]
Date: Fri Jan 19 2001 - 07:31:44 PST
Todd,
Since IBIS is a data transfer specification, not an analysis engine, I am
wondering how you run an "SI analysis in BOTH HSpice and IBIS". Especially
since many of the tools out there really have a spice or spice-like engine
underneath anyway.
But if you really mean when do we use behavioral models and when do we use
transistor level models, shouldn't that decision be based on the accuracy
and availability of each as model as well as how soon and how accurate you
need the answer? Simulations with detailed transistor level models are
always MUCH MUCH slower.
We have done some very accurate simulations that show some interesting but
real effects (simulation and lab measurement match) when those effects are
due the actual buffer such as the strength or timing of the pull up and pull
down transistors. But the IBIS data transfer specification does not make it
easy for you to model any effects that depend, not on the BUFFER but on how
that buffer is packaged. Can you say "simultaneous switching effects"?
The "B" in IBIS means buffer and you can take that buffer and put it inside
a package model developed using a field solver which has to be done with a
detailed transistor level model as well if you want to study SSN.
Aubrey Sparkman
Signal Integrity
[email protected]
(512) 723-3592
> -----Original Message-----
> From: Todd Westerhoff [mailto:[email protected]]
> Sent: Friday, January 19, 2001 7:14 AM
> To: [email protected]
> Subject: [SI-LIST] : SI analysis: IBIS vs. HSpice
>
>
> Hi all,
>
> I'm curious to know who out there is running SI analysis in
> BOTH HSpice and
> IBIS, and what your thoughts and experiences are (good and bad).
>
> I'm most interested in the strategies people use to ensure they're
> simulating the same circuit in both simulators, how people
> produce/validate
> models, and how well the two sets of simulation results are
> expected to
> correlate.
>
> Strategies for tool use (i.e. which kind of simulation do you
> use for which
> part of the design cycle) would also be a good topic for discussion.
>
> Comments (both public and private) are both welcome and appreciated.
>
> Todd.
>
>
> Todd Westerhoff
> SI Engineer
> Hammerhead Networks
> 5 Federal Street
> Billerica, MA 01821
> [email protected]
> ph: 978-671-5084
>
>
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