From: Peters, Stephen ([email protected])
Date: Fri Dec 15 2000 - 16:13:44 PST
Hi Henry:
If you are referring to the simulations used to extract data to build a
model, then including the package makes a BIG difference, at least in the
case of V-T tables. The V-T waveform tables are intended to capture the
switching and overlap characteristics of the pull-up and pull-down
transistors such that the simulator can extract the pertinent
characteristics of the CMOS transistors themselves. If you add in the dV/dt
and dI/dt effects of capacitance and inductance then all bets are off -- it
is very difficult (if not impossible) to de-imbed the transistor switching
data. Therefore, you should always take the [Ramp] and waveform data
without the effects of packaging included.
Regards,
Stephen Peters
Intel Corp.
-----Original Message-----
From: [email protected] [mailto:[email protected]]
Sent: Friday, December 15, 2000 3:24 PM
To: [email protected]
Subject: [SI-LIST] : IBIS model (Package parasitics)
Hi
In regard to IBIS models, it seems the recommendation is to remove the
parasitics of the package during simulation and include it in the
model file itself. I supposed an alternative would be to leave
it in during simulation and set the parasitics as zero in the
model file. Can someone please clarify the differences, if any,
between these two methods. Thanks in advance
-Henry Lee
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