[SI-LIST] : Clock Termination (WAS: Why can a resistor can reduce noise in output buffer)

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From: Andrew W. Riley III ([email protected])
Date: Fri Dec 01 2000 - 15:36:34 PST

"Michael Nudelman" wrote in terms that even I can understand...

> Because what you are doing is serilally terminating your output.
> Explained on fingers it is like this:
> Your signal (let's say - low-to-high transition), if a
> low-output-impedance driver is directly connected to a transmission
> line, will in its full amlitude travel to the end of that line, and
> then, the line being unterminated at the end (infinite load resistance)
> reflect back in its full amlitude; when it comes back to the source, it
> adds itself to the existing signal and you will see the signal double
> (that's your overshoot). Same for high-to-low transition - it will cause
> undershoot.
> Now, by plugging in a resistor in series with output, you divide the
> signal between the resistor and transmission line. Suppose, the resistor
> is equal to trans. line impedance. Than you divide it by half. So, half
> of your signal travels down the line, then reflects and goes back,
> adding to the existing signal (half added to half), making normal signal
> amplitude (no overshoot).
> In non-ideal situations you will see some overshoots/undershoots, but
> significantly reduced.

Very simply and well said!

"IMNSHBTAIAIBAO: In My Not So Humble But Technically Astute, Intuitive, And Irritatingly Blunt, Argumentative Opinion"[1]: I would argue one's intelligence is based more on the ability to enlighten the uneducated rather than one's unnecessary use of 'big words'. That being said, I understand most of what is posted to the SI-LIST <shameless and well-deserved pat on all SI-LIST members' backs>!
> Do not use this type of termination for clocks if you have more than one
> clock receiver on line; series termination for clocks is only good for
> point-to-point connection.
Is it simply because;
- the driver may see more than one reflection in the case of different trace lengths?
- there is more than one receiver, therefore more than one "half added to half" occurs?
If not, is it this easily explained? What about a resistor value calculated for one third of the signal amplitude (i.e.; two receivers per clock signal)?
Can you tell I have no SI tools? <shrug>I am not allowed a budget for one. 99% of what I know (which is not very much), I learn from you <another shameless pat on all SI-LIST members' backs>!
I thank all of you for your time,

[email protected]
[1]  The quote is from e-mail posted by Andrew J. Jenkins on 11-08-00 to Protel EDA User's Mailing List in the thread about the topic; Warnings to NT users of P99Se.

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