# RE: [SI-LIST] : D/W vs. S/H

Date: Thu Nov 30 2000 - 08:53:00 PST

Ken,
rate, trace length or if you were using stripline ,microstrip, etc. The edge
rate will greatly effect the amount of crosstalk seen by the victim trace
for a given setup. Also, the crosstalk will reach a maximum value when the
round trip time (2*Tpd) is equal to the edge rate (Tr). I was looking at
your example regarding the 5 mil trace width, 5 mil plane separation with
100mV (assume peak-to-peak). What is the trace length and edge rates used in
the calculation? Also you didn't mention the board material, i.e. FR4 is
assumed. The amount of crosstalk decreases by a factor of 4 for each linear
increase in spacing. Can you provide more details on how you arrived at your
values?

QLogic Corporation
[email protected]
Phone: (952) 932-4007
Fax: (952) 932-4037

-----Original Message-----
From: Ken Cantrell [mailto:[email protected]]
Sent: Thursday, November 30, 2000 10:15 AM
To: Loyer, Jeff W; [email protected]
Subject: RE: [SI-LIST] : D/W vs. S/H

Jeff,
I didn't see Doug's question, but in answer to yours, given the same plane
separation distance and allowable % crosstalk the wider the trace width the
closer (edge to edge) you can space the traces. Make yourself a chart of
trace width, plane separation (same permittivity of course), edge-to-edge
separation, and centerline-to-centerline (pitch). Group these parameters in
allowable % crosstalk, i.e., for a 3.3V system 100 mV is 3% crosstalk, and
change the trace width. Example: 5 mil traces, 5 mil plane separation, for
100 mV of crosstalk: edge-to-edge is 23 mils, pitch is 28 mils.
6 mil traces, 5 mil plane separation, 100 mV x-talk: edge-to-edge is 22
mils, pitch is 28 mils. The separation distance edge-to-edge decreases
linearly, a mil at a time in this example. Your CAD guys like to talk
pitch, so that's why I have the pitch column. Pitch varies with plane
separation given a constant trace width and allowable x-talk %. This way

Hope this helps,
Ken

-----Original Message-----
From: [email protected]
[mailto:[email protected]]On Behalf Of Loyer, Jeff W
Sent: Wednesday, November 29, 2000 1:55 PM
To: [email protected]
Subject: [SI-LIST] : D/W vs. S/H

Doug's query brought up a related question to my feeble mind...

Is there any reason to specify distance between traces relative to their
width? As far as I know, the most critical dimensions to consider are: 1)
distance between the edges of two traces, relative to 2) distance between
the trace and its ground plane(s). The width of the conductor is not a
significant factor, unless you're using center-to-center separation, where
you'll have to take into account the width. I don't understand why we
wouldn't specify S/H instead of D/W (see below).

______________________________________________________ GND
^
|
(H)
|
v
___________ <--- (S) ---> ___________ Signals traces
<-- (W) -->
<---------- (D) ---------->

Jeff Loyer
(253) 371-8093

-----Original Message-----
Sent: Wednesday, November 29, 2000 12:27 PM
To: [email protected]
Subject: [SI-LIST] : RE: Crosstalk Bus spacing

When determining the minimum spacing between traces on a digital bus, is it
best to setup the three traces as follows:(The design is using a stripline)

"A": Aggressor trace
"V": Victim trace
"A": Aggressor trace

------------------------------------------------------- Ground Plane layer
------(A)------ ------(V)------ ------(A)------ Trace layer, 0.5
ounce.
------------------------------------------------------- Ground Plane layer

Should both Aggressors be in-phase with each other or should one of them be
inverted to get the worst case crosstalk. I am simulating with both
applications and getting much more crosstalk on the victim trace when both
aggressors are in-phase.

The clock edge rate is 950pS and the trace width is set at w = 5 mils. The
Plane to trace layer spacing is 6.5 mils. This provides a nice 50 ohm trace
impedance.
The distance between traces is set at 5 mils (1w). I have been playing with
2w in the simulations as well.

Is it traditional to set the trace-to-trace spacing on the bus traces, i.e.
bits(0:x) for example, at 1w the trace width. The bus-to-adjacent traces
have been set for 2w spacing. The clock spacing is set for a 3w minimum.

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