From: Ritchey Lee ([email protected])
Date: Wed Nov 22 2000 - 09:39:00 PST
Thomas,
Thanks for looking this one up. It is a very good work on the topic of
cecoupling capacitors. Everyone who has the task of deciding on decoupling
should read this. Perhaps we could get Todd to post this paper on the UMR web
site.
Lee
Thomas Jackson wrote:
> I would like to call you attention to:
>
> "Power Bus Decoupling on Multilayer Printed Circuit Boards" by Hubing,
> Drewniak, Van Doren and Hockanson, published in the May 1995 IEEE
> Transactions on Electromagnetic Compatibility, Vol. 37, No.2.
>
> Among their conclusions is that "on printed circuit boards that do have
> internal power and ground planes, all decoupling capacitors are shared in
> the frequency range in which they are effective (typically below 200-300
> MHz), and the location of a decoupling capacitor on the board is relatively
> unimportant."
>
> It appears to be more important to have the shortest possible connections
> between the decoupling capacitors and the power and ground planes than where
> they are on the board.
>
> Thomas L. Jackson, P.E.
> Staff Product Development Engineer
> Network Access Development
> Systems Solutions Group
> FUJITSU MICROELECTRONICS, INC.
> 3545 North First Street
> San Jose, CA 95134-1804
> telephone: (408) 922-9574
> facsimile: (408) 922-9618
> http://www.fujitsumicro.com
>
> -----Original Message-----
> From: [email protected] [mailto:[email protected]]
> Sent: Monday, November 13, 2000 6:41 AM
> To: [email protected]; [email protected]
> Subject: Re: [SI-LIST] : deCoupling caps and there placement
>
> Keith,
> My approach is to put bypass capacitors as close as possible to the power
> pins
> on a chip. Whether we are using a multilayer card with ground and power
> planes,
> or a double-sided card with ground gridding, we will almost always have more
> connections to and more copper for ground than for any one supply voltage.
> Thus
> the path from a bypass capacitor to ground is usually shorter and wider than
> the
> path to a supply voltage. This results in:
> * Faster response by the capacitor, due to shorter transit time in the
> microstrip/stripline between the chip and the
> capacitor(s)--about 1/6 ns per inch for FR-4 boards.
> * More return-paths to the chip for the transient current, which reduces
> the
> inductance, impedance, L * dI/dt drop, and
> maybe radiated emissions by the magnetic fields of the various paths
> partially cancelling one another.
> * Smaller loop area for the transient currents, ditto.
>
> Since transient currents are my major concern, I try to put the highest
> frequency-response capacitors (typically 220pF NPO ceramics for clock and
> phase-locked loops (PLL's)) right next to their corresponding power pins.
> Then
> I put lower frequency-response capacitors (typically a 100nF X7R ceramic for
> each power pin or cluster of power pins) as close as possible to their
> corresponding power pins. Next I consider how to route traces/vias to bring
> power and ground to the power-pin/ground-pin/bypass capacitor cluster. If I
> can
> I will bring in power and ground right next to each other, but I don't worry
> too
> much if the power and ground connections are on opposite sides of a cluster.
>
> Depending on the complexity and package size of the chip, I will also put 1
> to 4
> bulk ceramic capacitors (typically 2.2uF Y5V ceramics) on each supply
> voltage
> within 1 inch of its power pins, trying to "surround" the chip. If I have
> a
> bunch of small chips in a small area, I may use just one bulk ceramic
> capacitor
> for the entire clump.
>
> Finally I put bulk aluminum electrolytic or tantalum capacitors (10uF and
> up):
> * Near the power connector(s) to a card.
> * Near power connectors to other cards/devices.
> * Near the corners of the supply-voltage domain.
> * Near "power hog" components, trying to have one within 2 inches of every
> power pin on that supply voltage ("coffee
> cup" rule).
>
> John Barnes Advisory
> Engineer
> Lexmark International
>
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