Re: [SI-LIST] : PCI Bus problem (an interesting one)

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From: Bo ([email protected])
Date: Mon Nov 20 2000 - 12:41:24 PST

Thanks for the reply Mike.

I agree with everything you said. I am doubting the models. I also know that
terminations should not be done on PCI bus (unless you are using ring topology
and even then only after carefull consideration). What I am seeing in the lab
is very very slow compared to what I see in simulations. If I can get
guarantee that I/O buffers would be slow all the time I would be very happy.
But I can't. The measurments may not be correct, but I am almost sure that
this is not the case.


--- Mike Mayer <[email protected]> wrote:
> [PCI problems simulation vs. real board]
> PCI is meant to be unterminated and so there can be overshoot and
> ringing. That said, I can think of several things that can cause
> differences between simulated and measured results:
> - models (of course)
> - only looking at typ simulation data (real board may be closer to
> min or max)
> - limited bandwidth of scope used to measure board or poor
> connection to board.
> --
> =============================================================================
> Mike Mayer
> [email protected]

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