From: Larry Miller ([email protected])
Date: Mon Nov 20 2000 - 10:13:33 PST
"there may be something in what you say."
After thinking it over, if the idea of linearity holds, I think I agree with
The National LVDS App Notes discuss this issue pretty well. And I stand by
my recommendation of the amount of skew you can stand.
> -----Original Message-----
> From: Charles Hill [SMTP:[email protected]]
> Sent: Monday, November 20, 2000 9:33 AM
> To: Miller, Larry [SC7:322:EXCH]; Khanh Le; [email protected]
> Subject: RE: [SI-LIST] : matched delay
> You said that mismatches cause duty cycle distortion. I don't understand
> the causal relationship. My reasoning goes as follows:
> Mismatches and reflections occur in transmission channels which are linear
> time invariant. A property of linear systems is no additional frequency
> components are created (intermodulation does not occur). For example, if
> a perfect square wave goes through a linear channel, only odd order
> harmonics go in and come out. Now duty cycle distortion implies even
> order harmonics are produced by a transmission channel with a perfect
> square wave input. But this is a contradiction since mismatches are a
> linear process which do not produce additional frequency components.
> The linear transmission channel affects positive and negative edges the
> same. These channels are characterized by an impulse response.
> That what it looks like to me. What do you think?
> Chuck Hill
> At 07:42 AM 11/20/00 -0800, Larry Miller wrote:
> As others have or will point out, mismatches cause loss of input
> level. They also cause duty cycle distortion (DCD), in my opinion. The
> practical result of this is that EMI is increased because the
> electromagnetic fields of the P and N signals cannot scrinch down and
> Remembering that LVDS was originally designed as a cable link
> technology, you might take some guidelines from similar speed wire
> For example, 100BASE-TX (which is actually 125 MHz, close enough to
> 155) the allowable DCD is 1/16 of a Unit Interval (0.5 ns out of 8 ns).
> Obviously, this gets tougher as you increase in frequency, but you
> probably ought to try for less than 50 ps.
> My $.02
> Larry Miller
> -----Original Message----- From: Khanh Le
> [SMTP:[email protected]] Sent: Monday, November 20, 2000 4:55 AM To:
> [email protected] Subject: [SI-LIST] : matched delay
> I am new to this forum and have an issue with the PCB layout of
> differential pair signals such LVPECL, LVDS and CML. Are there any rule of
> thumb for matched delay ? e.g. what should be the maximum difference in
> trace length between the p and n of the differential pair, where the
> signal is still considered to be within the safe margin. I have signals
> running at 155MHz, 622MHz, 1.25GHz and 2.5GHz. Thank you all. Khanh
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