RE: [SI-LIST] : Plane Splits Inspection

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From: abe riazi ([email protected])
Date: Mon Nov 13 2000 - 18:35:18 PST

Charles Grasso Wrote:

>The addition of multiple capacitors looks like an attractive option to cover the
>frequency range. But I wonder about the resonances that will occur between
>capacitors and the interconnect inductances. Has anyone modelled/tested
>effect yet?

Hi Charles:

To my knowledge, "stiching capacitors" have not been studied to the theoretical depth that "decoupling capacitors" have.
It is true that valuable work has been done in this area, papers have been written (reference 1) and reliable guidelines (for selection of the required quantities and values of stiching capacitors) have been formulated. But they have been mainly based on experimentation, trial and error.

Decoupling capacitors have been subject to more extensive investigations of both experimental and theoretical nature. In a publication (reference 2), Larry Smith utilized time and frequency domain analyses to determine capacitor values and quantities needed for maintaining power supply noise and impedance within specification. Doug Brooks (reference 3) has also shown that using multiple capacitors and mixing values can flatten the impedance response curve and prove beneficial towards achieving a low impedance over a wide frequency range.

As noted several times earlier today, decoupling capacitors have been also the central focus of a paper by Hubing et al. (reference 4). Equations 6 and 7 of that publications are:

Fs = 1/[2* PI *SQRT(L1C1)] (Equation 6)

Fp = Fs * SQRT[1+ nC1/Cb] (Equation 7)

The first equation yields the series resonance frequencies (i.e. the zeros in the impedance vs. frequency plots) and the latter equation outputs parallel resonances (i.e. the undesirable poles).

Study of above two equations and modeling metholdology described in reference 4, has led me to the following conclusion:

It can be considerably more difficult to determine the resonant and anti-resonant frequencies for stiching capacitors (involving split Power and Ground planes) than for case of decoupling capacitors (connecting to continuous planes), as the inductive contribution can be signifcantly complicated to ascertain when plane discontinuities exist.

[1] L. Ritchey, "Examining Rules of thumb", Printed Circuit Design, January 2000, PP. 36-38.
[2] L. D. Smith, "Decoupling Capacitor Calculations for CMOS Circuits" IEEE Electrical Performance of Electrical Packaging (EPEP) Conference 1994.
[3] D. G. Brooks, "ESR and Bypass Capacitors", printed Circuit Design, June 2000, PP. 30-32.
[4] T.H. Hubing, J.L. Drewniak, T.P. Van Doren and D.M. Hockanson, "Power Bus Decoupling on Multilayer Prined Circuit Board", IEEE Transactions on Electromagnetic Compatibility, Vol 37. No. 2, May 1995, PP. 155 - 166.

Best Regards,

Abe Riazi

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