Re: [SI-LIST] : effect of trace width on the performance

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From: Bill Owsley ([email protected])
Date: Wed Nov 01 2000 - 10:35:04 PST

not much clarification here...
but there is an indication that you are not measuring anything, but simply
doing a power on functional test at low voltage. quantum leap to get to
ground bounce from there...
There is plenty of ground Cu, but if your power Cu at 2 x 0.5 layers is not
enough for the current requirements, you may have the complement of ground
bounce - power sag, especially at low V.

At 09:35 AM 11/01/2000 -0800, Muhammad S. Sagarwala wrote:
>Here is the board stackup...
>--------------- Top layer with all the active componenets
>--------------- Ground layer
>--------------- Vdd1 layer
>--------------- Ground layer
>--------------- Vdd2 layer
>--------------- Ground layer
>--------------- Signal Layer
>--------------- Ground layer
>--------------- Signal layer
>--------------- Ground layer
>--------------- Signal layer
>--------------- Ground layer
>--------------- Signal layer
>--------------- Ground layer
>--------------- Bottom layer (with decoupling caps and other discretes)
>Just to sum it up.. there are two power layers pretty close to the device.
>All the signals are routed as strip lines. The decoupling caps were
>placed on the bottom
>side of the board because of space limitations on the top side. All the
>caps are x7r (dielectric).
>The layer stackup (arrangement) is exactly the same for both boards. The
>is the thickness of the boards. Since traces on both boards are 50 ohms
>impedence but since one board has 9 mil wide traces while the other has
>7.5 mil
>wide traces therefore the board with 9 mil wide traces is thicker. Also
>the board with
>9 mil wide traces has 1 oz copper on all power/ground planes.
>The reason I suspect ground bounce is the culprit in this case
>(1) since we followed the same routing rules on both boards so cross talk
>could not be an issue
> (because if it were, we would see it in the first board i.e. the one
> with 9 mil wide traces)
>(2) since the boards are made of Cynate Ester (loss tangent very low)...I
>do not think dielectric losses are a major
> problem.
>(3) one of the tests that we performed was to operate the devices near the
>Vil threshold. We found that the board with
> 9 mil wide traces and 1oz. power planes had no problems while the
> board with 7.5 mil wide traces did not work.
>I hope this clarifies everything....
>>-----Original Message-----
>>From: Scott McMorrow <<mailto:[email protected]>[email protected]>
>>To: Muhammad S. Sagarwala
>><<mailto:[email protected]>[email protected]>
>>Date: Wednesday, November 01, 2000 9:12 AM
>>Subject: Re: [SI-LIST] : effect of trace width on the performance
>>It would be helpful to the group if you were to provide a picture of
>>the before and after of the stackups. It seems that we are all guessing
>>about what your configuration really is at this time. I would also include
>>the location of all ground and power planes.
>>Also, a list of all things which have changed from the previous fab
>>to this one would be helpful. This way we can eliminate possible
>>causes of your problem.
>>Finally, why do you think it is a ground bounce problem?
>>Do you have root cause for your failures?
>>Scott McMorrow
>>Principal Engineer
>>SiQual, Signal Quality Engineering
>>18735 SW Boones Ferry Road
>>Tualatin, OR 97062-3090
>>(503) 885-1231
>>"Muhammad S. Sagarwala" wrote:
>>> Thanks a lot for your input Mike... The stackup is the same but the
>>> dielectric thickness is different...I mean the arrangement of the
>>> planes is the same but the thickness of thedielectric (and hence the
>>> boards is different).. The lengths of the traces on these boards is
>>> between 7-10 inches. One more question...I am suspecting ground
>>> you think that copper weight and trace widths could play a
>>> major role... Muhammad
>>>>-----Original Message-----
>>>>From: Michael Nudelman
>>>><<mailto:[email protected]>[email protected]>
>>>>To: Muhammad S. Sagarwala
>>>><<mailto:[email protected]>[email protected]>
>>>>Cc: <mailto:[email protected]>[email protected]
>>>><<mailto:[email protected]>[email protected]>
>>>>Date: Wednesday, November 01, 2000 6:18 AM
>>>>Subject: Re: [SI-LIST] : effect of trace width on the performance
>>>> Muhammad:
>>>>1. If your stackup is the same (dielectr. thicknesses etc) - then how
>>>>does the impedance stays the same with traces' widths changed? (if it
>>>>is different, than it is possible.)
>>>>2. How long are the traces? In case of 7.5 mils your skin effect losses
>>>>increase and at certain lengths they may impaire your signal quality.
>>>>3. The pwr plane copper oz are not that important. Or at least I think
>>>>so :-)))
>>>>"Muhammad S. Sagarwala" wrote:
>>>>> Hi SI Gurus, I am in a big problem. I designed two boards which are
>>>>> pretty much the same.The changes between them are: (1) One has traces
>>>>> that are 7.5 mils wide and the other has 9 mils wide traces (both
>>>>> have a characteristic impedence of 50 ohms)(2) The one that has 9 mil
>>>>> wide traces has 1 oz copper for the pwr planes and the one with 7.5
>>>>> mil wide traces has 0.5 oz. copper on pwr planes. The stackup is
>>>>> pretty much the same.The Frequency of signals on the boards is 400
>>>>> Mhz.The decoupling scheme on both boards is pretty much the
>>>>> same. The problems is the board with 9 mil wide traces and 1oz.
>>>>> copper is performing very good and the other board with 7.5 mil
>>>>> widetraces and 0.5 oz. copper is behaving very very bad. My question
>>>>> is "do you think these changes make a big difference or is there
>>>>> another variable(s) that I am missing?????" Comments suggestions are
>>>>> most welcome....(I need to be sure before I make a decision to respin
>>>>> the board ) Muhammad Muhammad S. Sagarwala
>>>>>Schlumberger SABER
>>>>>Ph. (408) 586 7065
>>>>>Fax (408) 586 4668

Bill Owsley, [email protected]
919) 392-8341

TMBU Compliance
Cisco Systems
7025 Kit Creek Road
POB 14987
RTP. NC. 27709

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