From: Lynne Green ([email protected])
Date: Thu Oct 12 2000 - 18:38:33 PDT
Doug-
Use a pre-layout simulator to test various distances and check
pin-to-pin delays, so you can go into layout with the proper
length and termination constraints.
Speed varies about +/- 5% in FR4, depending on eps_r, which in
turn depends on manufacturing process. Add another 5% or so
variation with dielectric thickness.
Also, speed can be different for inner layers vs. outer layers,
depending on the number of signal layers between planes, and
on whether you have any surface dielectrics (such as a solder
mask layer).
Check out the HyperLynx Stackup Editor to see how significant
the variations might be for your boards.
http://www/hyperlynx.com
- Lynne
Dr. Lynne Green
Technical Marketing Engineer
Innoveda
14715 NE 95th St, Suite 200
Redmond, WA 98052
425-497-5081
FAX 425-881-1008
[email protected]
http://www/innoveda.com
-----Original Message-----
From: [email protected]
[mailto:[email protected]]On Behalf Of Ron Miller
Sent: Thursday, October 12, 2000 8:49 AM
To: 'JNH'; Doug Hopperstad
Cc: [email protected]
Subject: RE: [SI-LIST] : RE: PCI routing rules
Try 85 ps per inch one way for FR4.
which is closer to 6 inches per ns.
Ron Miller
> -----Original Message-----
> From: JNH
> Sent: Wednesday, October 11, 2000 4:59 PM
> To: Doug Hopperstad
> Cc: [email protected]
> Subject: RE: [SI-LIST] : RE: PCI routing rules
>
> Doug,
> Based on rule of thumb, the propagation delay of PCB is about 4 inch/ns
including loading, the round trip propagation delay for PCI speedway has to
be 10ns. Therefore, the maximum trace length for PCI is 4 inch/ns x 10ns /
2 = 20 inch.
>
> I hope it helps to you.
>
> Best Regards,
>
> John Lin
> Quanta Computer Inc.,Taiwan, R.O.C.
> Email: [email protected]
> Tel: 886+3+3979000 ext. 5183
>
>
> -----Original Message-----
> From: Doug Hopperstad [ <mailto:[email protected]>]
> Sent: Thursday, October 12, 2000 3:18 AM
> To: '[email protected]'
> Subject: [SI-LIST] : RE: PCI routing rules
>
>
> Does anyone have any information on PCI routing rules. I am trying to
> determine the maximum trace length between PCI devices and have been
> struggling with the 10nS time margin. Is there a formula to determine the
> maximum trace length between PCI devices?
>
> Doug Hopperstad
> QLogic Corporation
> [email protected]
>
>
>
>
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