From: Sunil Kumar ([email protected])
Date: Wed Oct 11 2000 - 23:41:55 PDT
Hello everybody.
I am measuring cycle-to-cycle jitter in clock in a system, where clock
(PECL, 50MHz) is going from one PCB (card) to other through twinax
cable. In the second card clock is converted into TTL and then distributed
to various ICs. I am looking at the clock just before the PECL-to-TTL
convertor. Both the cards are in the same backplane. The system is
equiped with a set of fans for cooling, which are kept below the card
frame. Now what I have observed is, when the fans are not on, jitter is
much much less in comparision of the jitter when fans are on. I think, the
fans are generating EMI, which is disturbing the planes in the backplane
and the cards, and hence jitter is increased. Any explanations?
One more thing which I have observed is, the PECL-to-PECL clock
fanout buffer (no PLL inside) is reducing jiiter (with fans off), i.e.
jitter at input is more than that at output. Can anybody explain this?
Is there any PECL-to-TTL clock fanout buffer which adds very low
jitter? The PECL-to-TTL buffer which I am using, is adding lot's of
jitter.
Thanks
Sunil Kumar
Senior Research Engineer
ATM Group
C-DOT
Bangalore-560052
INDIA
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