RE: [SI-LIST] : JEDEC HSTL and SSTL_2 standards compliance

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From: Todd Westerhoff ([email protected])
Date: Tue Oct 10 2000 - 14:16:14 PDT

Okay - so, the idea of reducing the number of power supplies certainly makes

But there's still the isssue of using multiple voltages in place of what's
supposed to be a standard. What happens if a user wants to use two
different "HSTL" parts together, one of which is designed for 1.5 volt VDDQ,
and the other for 1.8 volts? Doesn't that create a real problem with Vref
and noise margins?

So, it seems that there is 1.8 volt HSTL, and 1.5 volt HSTL. A stupid
question perhaps, but: are there any others?



Todd Westerhoff
Principal Signal Integrity Engineer
Hammerhead Networks
5 Federal Way
Billerica, MA 01821

-----Original Message-----
From: Bill Cohen [mailto:[email protected]]
Sent: Tuesday, October 10, 2000 2:25 PM
To: [email protected]; [email protected]
Subject: Re: [SI-LIST] : JEDEC HSTL and SSTL_2 standards compliance

Todd Westerhoff wrote:

> Concerning HSTL (JEDEC EIA/JESD8-6):
> The standard specifies that the technology is "VDD independent" (makes
> sense, as long as the output buffers are properly designed), and that VDDQ
> supply should be in the range of 1.4 to 1.6 volts.
> Why then, are some vendors supplying parts that call for a 1.8 volt VDDQ
> supply and calling them HSTL?

The 1.8V VDDQ is to reduce power supplies on the board. Usually an ASIC
contains 3.3V (for LVTTL) and sometimes 2.5V (for SSTL). The core is run
at 1.8V for fast/low power logic. If another 1.5V voltage was added then
the chip would require 4 sepatate power supplies. If the HSTL was driven
at 1.8V then the core logic and HSTL I/O would be able to share the same
power supply. HSTL run at 1.8V can usually interface to 1.5V HSTL with
little trouble. Some adjustment of VREF may be necessary.

Bill Cohen
Toshiba America
[email protected]

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