[SI-LIST] : JEDEC HSTL and SSTL_2 standards compliance

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From: Todd Westerhoff ([email protected])
Date: Tue Oct 10 2000 - 10:46:27 PDT

Hi everyone,

We've been going though a number of device data sheets and noticed a few
things that puzzled us. I didn't find a suitable thread in the archives, so
I thought I'd ask for comment:

Concerning HSTL (JEDEC EIA/JESD8-6):

The standard specifies that the technology is "VDD independent" (makes
sense, as long as the output buffers are properly designed), and that VDDQ
supply should be in the range of 1.4 to 1.6 volts.

Why then, are some vendors supplying parts that call for a 1.8 volt VDDQ
supply and calling them HSTL?

Concerning SSTL_2 (JEDEC EIA/JESD8-9):

Section 2.1 (Voltage Levels), Note 1 states that "under all conditions, VDDQ
must be less than or equal to VDD".

Does anyone know the reasoning behind this? Why should the value of VDD
matter, as long as the output buffers are designed correctly?

And, of course - back to actual practice - if the spec if true, why are
vendors supplying parts calling for a 1.8 volt VDD and 2.5 volt VDDQ?

Thoughts and insights are greatly appeciated.



Todd Westerhoff
Principal Signal Integrity Engineer
Hammerhead Networks
5 Federal Way
Billerica, MA 01821

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