From: Michael Nudelman ([email protected])
Date: Wed Sep 27 2000 - 14:52:46 PDT
Well, this book was recommended to me by a person who I inherited a design
from, that I had to convert to use FibreChannel using ISP2100 chips from
QLogic; these chips had PCI interface to connect them to memory etc. He
praised that book over others (and I did order another book too) and I found
he was right. Unlike other this one was very practical.
I designed (first time in my life) PCI bus, that worked from the start.
Despite all the crap I put into my first CPLD edition of the PCI arbiter
:-))))
Mike.
"Peterson, George W" wrote:
> Thanks Mike. $32 seems like a fair price if it's as good as you say...
> --George
>
> > -----Original Message-----
> > From: Michael Nudelman [mailto:[email protected]]
> > Sent: Wednesday, September 27, 2000 1:31 PM
> > To: [email protected]; [email protected]
> > Subject: Re: [SI-LIST] : PCI speedway
> >
> >
> > George, Angelo:
> >
> > This is the link to the book.
> >
> > http://www.amazon.com/exec/obidos/ASIN/0201309742/o/qid=970086
> > 193/sr=2-2/102-6005797-8514538
> >
> > [email protected] wrote:
> >
> > > Hi Mike, Hi Erich
> > > Thank for your answers. Of coarse I am interested the name
> > of the book.
> > > I am following the "classic? topology suggests by EDN
> > article and HSPICE
> > > internet manual: a band of PCI traces with PCI devices on
> > both sides connect
> > > with short stubs to speedway. In my previous designs I used
> > the daisy chain
> > > topology for high speed non PCI bus, with good results.
> > Using the daisy chain
> > > solution in this new PCI design, the bus length is more
> > than 15inch. So I would
> > > like to find a skilled guideline about the speedway.
> > > Do you include the test connector capacitive load in your
> > capacitive budget for
> > > PCI transmission line ?
> > > Sorry for my English.
> > >
> > > Thanks again
> > > Ciao Angelo
> > >
> > > Michael Nudelman <[email protected]> on 27/09/2000 14.15.53
> > >
> > > Please respond to Michael Nudelman <[email protected]>
> > >
> > > To: Angelo Li Quadri Cassini/AETHRA@AELOTUS
> > > cc: [email protected]
> > > Subject: Re: [SI-LIST] : PCI speedway
> > >
> > >
> > --------------------------------------------------------------
> > ----------
> > >
> > > I'll look up the name of the book I have at home; this is
> > the best book for the
> > > PCI
> > > design I ever saw and I used it in my design.
> > >
> > > The PCI bus is fairly tolerant at 33MHz. I stretched it for
> > almost 18 inches
> > > with
> > > one north bridge and it worked reliably, though it was a
> > necessity. If you can
> > > use a
> > > "slave" bridge to cut the bus in half (again, if your bus
> > becomes very long) -
> > > do
> > > it.
> > >
> > > The layout is simple - fairly uniform bus, no stubs;
> > de-scewed clock, for which
> > > I
> > > personally would recommend Cypress Robo-Clock drivers.
> > >
> > > Advise: do put a test header for a digital analyzer on all
> > PCI signals; PCI
> > > protocol
> > > is fascinating and sometimes without analyzer you won't get far.
> > >
> > > Mike.
> > >
> > > [email protected] wrote:
> > >
> > > > Hi , Guy
> > > >
> > > > somebody can help me to looking for real example to PCI
> > speedway layout and
> > > > component placing ?
> > > > I know the EDN article (november 1994) about this issue
> > and the abstract to
> > > Star
> > > > ?Hspice manual.
> > > >
> > > > thanks for your help
> > > > Ciao Angelo
> > > >
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