From: Michael Nudelman ([email protected])
Date: Wed Sep 27 2000 - 13:31:25 PDT
George, Angelo:
This is the link to the book.
http://www.amazon.com/exec/obidos/ASIN/0201309742/o/qid=970086193/sr=2-2/102-6005797-8514538
[email protected] wrote:
> Hi Mike, Hi Erich
> Thank for your answers. Of coarse I am interested the name of the book.
> I am following the "classic? topology suggests by EDN article and HSPICE
> internet manual: a band of PCI traces with PCI devices on both sides connect
> with short stubs to speedway. In my previous designs I used the daisy chain
> topology for high speed non PCI bus, with good results. Using the daisy chain
> solution in this new PCI design, the bus length is more than 15inch. So I would
> like to find a skilled guideline about the speedway.
> Do you include the test connector capacitive load in your capacitive budget for
> PCI transmission line ?
> Sorry for my English.
>
> Thanks again
> Ciao Angelo
>
> Michael Nudelman <[email protected]> on 27/09/2000 14.15.53
>
> Please respond to Michael Nudelman <[email protected]>
>
> To: Angelo Li Quadri Cassini/AETHRA@AELOTUS
> cc: [email protected]
> Subject: Re: [SI-LIST] : PCI speedway
>
> ------------------------------------------------------------------------
>
> I'll look up the name of the book I have at home; this is the best book for the
> PCI
> design I ever saw and I used it in my design.
>
> The PCI bus is fairly tolerant at 33MHz. I stretched it for almost 18 inches
> with
> one north bridge and it worked reliably, though it was a necessity. If you can
> use a
> "slave" bridge to cut the bus in half (again, if your bus becomes very long) -
> do
> it.
>
> The layout is simple - fairly uniform bus, no stubs; de-scewed clock, for which
> I
> personally would recommend Cypress Robo-Clock drivers.
>
> Advise: do put a test header for a digital analyzer on all PCI signals; PCI
> protocol
> is fascinating and sometimes without analyzer you won't get far.
>
> Mike.
>
> [email protected] wrote:
>
> > Hi , Guy
> >
> > somebody can help me to looking for real example to PCI speedway layout and
> > component placing ?
> > I know the EDN article (november 1994) about this issue and the abstract to
> Star
> > ?Hspice manual.
> >
> > thanks for your help
> > Ciao Angelo
> >
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