RE: [SI-LIST] : hold time dilemma

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From: [email protected]
Date: Tue Aug 29 2000 - 13:02:23 PDT

Perhaps the easiest way to think about resolving the hold time dilemma is to
look at the difference in hold time on either end of a bi-dir bus. if the
Tco mins are equal, then you can skew the clock to half the hold time
difference to minimize the problem. If the Tco mins are different, and you
are lucky, the I/O with the long hold time will also have a larger Tco min.
Again you can benifit from half the difference. On the other hand, Murphy's
law may apply and the difference will be reversed which will cancel your
ability to skew the clocks.

Good Luck,

Aubrey Sparkman
Signal Integrity
[email protected]
(512) 723-3592

> -----Original Message-----
> From: Peterson, James F (FL51) [mailto:[email protected]]
> Sent: Tuesday, August 29, 2000 1:21 PM
> To: Chris Hansen; Ingraham, Andrew; [email protected]
> Subject: RE: [SI-LIST] : hold time dilemma
>
>
> EXACTLY RIGHT. It's a bi-dir bus that is not helped with a 1
> ns delay on one
> of the clocks.
> -jim
>
> -----Original Message-----
> From: Chris Hansen [mailto:[email protected]]
> Sent: Tuesday, August 29, 2000 1:58 PM
> To: Ingraham, Andrew; [email protected]
> Subject: RE: [SI-LIST] : hold time dilemma
>
>
> Remember, this is probably a bidirectional bus, so delaying
> the SDRAM clock
> could have the bad effect of creating a hold time violation
> when driving
> from the processor.
>
>
> -----Original Message-----
> From: Ingraham, Andrew [mailto:[email protected]]
> Sent: Tuesday, August 29, 2000 1:17 PM
> To: [email protected]
> Subject: RE: [SI-LIST] : hold time dilemma
>
>
> > I have a synchronous ram with a tco (clk to valid out) of
> (1ns,3ns). I
> > have
> > a processor with a tHold of 1ns (min). Taking the min. tco
> for a hold time
> > analysis gives me 0ns of margin. Any clock skew at all
> between the ram and
> > the processor makes this fail timing analysis.
>
> Try delaying the clock to the SRAM by a nanosecond or so;
> it's less severe
> than the 5+ ns equivalent delay of inverting the clock.
>
>
>
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