From: [email protected]
Date: Tue Aug 29 2000 - 11:56:14 PDT
8/29/00 12:59:58 PM, "Peterson, James F (FL51)" <[email protected]>
>Here's my hold time dilemma/question :
>I have a synchronous ram with a tco (clk to valid out) of (1ns,3ns). I have
>a processor with a tHold of 1ns (min). Taking the min. tco for a hold time
>analysis gives me 0ns of margin. Any clock skew at all between the ram and
>the processor makes this fail timing analysis.
>It used to be that one solution was to invert the clock to the ram, but
>these days it's hard to justify cutting the board's settling time by 50% (At
>100MHz, you've gone from a starting budget of 10ns to one of 5ns).
>What are some you high speed board designers doing about this?
I'm not sure I understand what Jim's problem is. I've just completed an FPGA-based
design that uses SDRAM, so this stuff is all fresh in my head. Sync SRAM seems
I'm looking at the data sheet for a Micron 2Mb ZBT SRAM part. The memory has some
given clock-to-out time -- in this case, 7.5 ns. If the address and command signals
are registered on clock tick 1, the data becomes valid 7.5 ns later, or 2.5 ns
before the next edge, tick 2, of Jim's 100 MHz clock.
There should also be some minimum data output hold time spec. To use the spec from
Micron, say tOH is 3 ns. Therefore, the data will start to go away 3 ns after clock
tick 2. Clock tick 2 is when the processor should be registering the data input.
So, using these numbers, and Jim's 100 MHz clock, at his processor's data bus pins,
he has 2,5 ns (minus flight time) setup and 3 ns hold time (flight time helps here).
In other words, assuming low-to-zero clock skew (achievable with attention to board
layout and PLL clock drivers), there's no problem.
Or am I out to lunch here?
-- --------------------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N. Cherry Ave Tucson, AZ 85719 520-318-8191 [email protected]
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