RE: [SI-LIST] : hold time dilemma

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From: Chris Hansen ([email protected])
Date: Tue Aug 29 2000 - 10:57:40 PDT


Remember, this is probably a bidirectional bus, so delaying the SDRAM clock
could have the bad effect of creating a hold time violation when driving
from the processor.

-----Original Message-----
From: Ingraham, Andrew [mailto:[email protected]]
Sent: Tuesday, August 29, 2000 1:17 PM
To: [email protected]
Subject: RE: [SI-LIST] : hold time dilemma

> I have a synchronous ram with a tco (clk to valid out) of (1ns,3ns). I
> have
> a processor with a tHold of 1ns (min). Taking the min. tco for a hold time
> analysis gives me 0ns of margin. Any clock skew at all between the ram and
> the processor makes this fail timing analysis.
 
Try delaying the clock to the SRAM by a nanosecond or so; it's less severe
than the 5+ ns equivalent delay of inverting the clock.

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