From: Ingraham, Andrew ([email protected])
Date: Tue Aug 29 2000 - 10:17:16 PDT
> I have a synchronous ram with a tco (clk to valid out) of (1ns,3ns). I
> a processor with a tHold of 1ns (min). Taking the min. tco for a hold time
> analysis gives me 0ns of margin. Any clock skew at all between the ram and
> the processor makes this fail timing analysis.
Try delaying the clock to the SRAM by a nanosecond or so; it's less severe
than the 5+ ns equivalent delay of inverting the clock.
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