RE: [SI-LIST] : Decoupling capacitors (again!)

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From: Istvan Novak - Board Design Technology ([email protected])
Date: Wed Aug 16 2000 - 10:27:27 PDT

Further to the point that Larry mentioned about the importance of thin dielectrics, you
may want to know that the Embedded Decoupling Capacitance Consortium will have its next
conference on this coming Monday, see:

Also, there are related articles published in the IEEE Transactions on Advanced
packaging, check out:

- volume 23, number 2, May 2000, several papers in the Contributed papers section, see
e.g., starting at page 293

- volume 23, number 3, August 2000, starting at pages 340 and 353

Istvan Novak
SUN Microsystems
        X-Unix-From: [email protected] Tue Aug 15 20:11:52 2000
        Date: Tue, 15 Aug 2000 16:57:25 -0700 (PDT)
        From: Larry Smith <[email protected]>
        Subject: RE: [SI-LIST] : Decoupling capacitors (again!)
        To: [email protected]
        MIME-Version: 1.0
        Content-MD5: sAZNo3fTcIQGdjDo1e8joA==
        Martin has a good question on decoupling and Pat has contributed some
        good comments on the subject. The most common complaint that I hear
        about this decoupling methodology is that it requires the use of too
        many capacitors! Please allow me to make a few comments that may
        First of all, we need to carefully distinguish between a power
        distribution problem and an SSN (simultaneous switch noise) problem.
        Anytime there are IO or transmission lines involved, it is probably an
        SSN problem. The two problems are closely related, but if we don't
        make a careful distinction, we will greatly over estimate the number of
        capacitors required.
        To determine the number of discrete decoupling capacitors required in a
        system, we first calculate the target impedance. For Martin's problem
        we can get a good estimate from the clock frequency and capacitance
        load. The system runs at 100 MHz and there is 1.5 nF of capacitance
        that may be charged up to 3.3V or discharged to ground every clock
        cycle. Q = CV, so we have 1.5nF*3.3V = 4.95 nCoulombs that may flow
        every clock cycle. I = dQ/dt, so we have 4.95 nCoul/10nSec = .495 amps
        average current. Most systems can tolerate a 5% supply, so the target
        impedance is Zt = Vdd*5%/I = 3.3*.05/.495 = 333 mOhms. (If there is
        more than just IO circuitry hanging on the 3.3V supply, the target
        impedance should be lower.)
        333 mOhms is much higher than the 20 mOhm target impedance calculated
        below. The error has come because the power distribution problem was
        mixed up with an SSN problem. SSN is concerned with edge rates, but
        the power distribution target impedance is associated with average
        currents. It will be easy to maintain 333 mOhm impedance out to more
        than 100 MHz with about a dozen carefully chosen capacitors. This is
        all that is needed for this power distribution problem and is
        consistent with the intuition that experienced engineers have regarding
        the number of capacitors required. The decoupling capacitor
        methodology gives a good way to optimize the chosen capacitors and
        guarantee there are no high impedance frequencies up to several hundred
        MHz. This becomes necessary on larger systems where we really have to
        maintain 10 mOhms or less up to high frequencies.
        As Ray mentioned in a previous note, it is very difficult to maintain a
        low target impedance above 200 MHz using discrete capacitors. The 1 nH
        mounting inductance for a discrete capacitor contributes more than 1
        Ohm of impedance. You have to put 50 of them in parallel to get to 20
        mOhms at 200 MHz. If you want 20 mOhms at 1GHz, it takes 5x more than
        that! With low ESR capacitors, it is possible to target certain
        critical frequencies above 200 MHz using the resonance technique. But
        the number of discrete capacitors required to maintain a flat 20 mOhm
        impedance up to 1 GHz is prohibitively large, and really not necessary
        on any of the systems that I work on.
        The answer to the SSN problem is thin dielectric power planes. At 1
        GHz, 8nF gives an impedance of 20 mOhms (1/jwC). 36 square inches (6x6
        inches) of a pair of power planes separated by 4 mils of FR4 gives this
        capacitance. If our SSN problem is centered within this area, this
        capacitance will be available within a 1 nSec rise time. It really
        does not make sense to use discrete decoupling capacitors to deal with
        SSN noise associated with today's fast edge rates. Capacitance between
        PCB and package power planes and capacitance embedded on chip are the
        best defenses against SSN.
        One more comment, target impedance is really too simplistic of a
        concept to be useful for the SSN problem. To really deal with the SSN
        problem, you have to know which way the driver is switching (high or
        low) and whether the transmission line return current flows mostly on
        the Vdd plane or Ground plane in order to make SSN calculations (yes,
        it makes a big difference!). There is another paper on the same web
        site as the decoupling capacitor paper. Check out "Simultaneous Switch
        Noise and Power Plane Bounce for CMOS Technology" on:
        Larry Smith
        Sun Microsystems
> From: "Zabinski, Patrick J." <[email protected]>
> To: [email protected]
> Subject: RE: [SI-LIST] : Decoupling capacitors (again!)
> Date: Tue, 15 Aug 2000 10:40:50 -0500
> MIME-Version: 1.0
> Martin,
> I can't offer much advice, but I can possibly offer some
> comfort in that I've had the same problem. For one design
> I was recently involved in, I tried to follow the same
> approach/theory, and the end result was that I needed
> 80 decoupling capacitors per ASIC (to maintain 10%
> dV), and I had 32 ASICs per board (>2500 caps per board!).
> After having others verify
> my numbers/calculations, I took close look and realized
> the caps would consume more board space than the ASICs.
> I could not justify, believe, or afford this, so I
> ended up backing down and relying on my old rules of
> thumb (BTW: I hate rules of thumb, but I sometimes
> use them when I have no better way). The board works
> fine with only 12 caps per ASIC.
> Looking back, I can see three possible reasons why the approach you
> and I took is not quite complete:
> * component packaging effects are not taken to
> account. Not definite on this, but I believe
> a poor package would probably negate any capacitance
> you might have on the board.
> * the board's self-impedance. I believe Larry's
> approach addresses this as effective increase
> in inductance, but the ground/power plane itself
> does offer a low-impedance capacitance. Regardless
> if you have any discrete caps on or not, the planes
> offer some inherent, built-in capacitance.
> * most (all?) dI/dt effects are self-limiting.
> For the calculations you used, they assumed
> dV=0.0. However, if dV>0, then dI/dt will
> be reduced all on its own. I don't have any
> data or theories on how much, but dI/dt
> is likely to be reduced from what you
> predicted (also tied into/related to the
> first issue about packaging).
> Sound reasonable? Comments?
> Anyway, I sympathize and hope you find a solution. If you
> do, please share.
> Pat
> > -----Original Message-----
> > From: Martin J Thompson [mailto:[email protected]]
> > Sent: Tuesday, August 15, 2000 9:49 AM
> > To: <"[email protected]"
> > Subject: [SI-LIST] : Decoupling capacitors (again!)
> >
> >
> > Hi all, this is my first time posting here, although I've
> > been lurking for a while.
> >
> > My problem is figuring out the decoupling requirements for
> > this system:
> > FPGA, DSP, 6 SDRAMS, 2 flash, DPRAM, clock frequency is 100MHz.
> >
> > According to my calculations, my I/O's need to drive a total
> > of about 1.5nF of I/O and trace capacitance.
> > To achieve the 0.5ns edges that the FPGA will drive (3.3V
> > supply) it looks like I need dI=4amps. This is assuming that
> > 50% (is this typical?) of the I/O's toggle each cycle. (dI=0.5Cdv/dt)
> >
> > To achieve a dV of < 0.1V this implies a target impedance of
> > around 20mohm, flat up to 1GHz! (Z=dv/di)
> >
> > This then seems to need around 500-800 decouping caps spread
> > around, which is an order of magnitude more than I've ever
> > used in the past. This is the first time I have taken a
> > 'design' approach to the problem, but the previous boards
> > have worked, using various rules of thumb.
> >
> > Is this sort of number of caps to be expected in this sort of
> > system, or can anyone see any sillies in my understanding (or
> > even in the sums!)?
> >
> > Now, if I don't get right out to 1GHz, the edges will suffer,
> > but that wouldn't necessarily matter if they stayed below
> > 1-1.5ns. Or would this cause the supply to droop elsewhere?
> >
> > As you might gather from the analysis above I've read Larry
> > Smith and co's paper on decoupling design, which states that
> > a flat target impedance is indicated. If I can analyse my
> > application enough, can I then shape the Ztarget vs frequency
> > to make life easier?
> >
> > Many thanks for your time, any help greatly appreciated,
> >
> > Martin
> >
> >
> >
> > TRW Automotive Advanced Product Development,
> > Stratford Road, Solihull, B90 4GW. UK
> > Tel: +44 (0)121-627-3569
> > mailto:[email protected]
> >
> >
> >
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Istvan Novak Sun Microsystems, Inc.
[email protected] Workgroup Servers, BDT Group,
                        One Network Drive, Burlington, MA 01803
                        Phone: (781) 442 0340

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