Re: [SI-LIST] : RE : LVDS Skew

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From: [email protected]
Date: Thu Aug 10 2000 - 12:32:32 PDT

As far as I know, a differential receiver is still a differential receiver.
Even if the individual trace voltages of a differential pair do NOT
transition during the same time frame (as aptly illustrated by Scott's paper
demonstration), a data rate (double-edge clocked or not) whose time period is
substantially longer than the signal rise time will function properly (from
the logic standpoint), but can create potential EMI problems.

To clarify using Scott's example, applying a peak-to-peak amplitude of 100%
(or use mV if you like) to EACH signal (centered about some DC level of
course), you will find the DIFFERENTIAL signal to also be 100% (or mV)
peak-to-peak. For perfect switching synchronism (i.e., no skew with
crossover at the centers of both signal transitions), the transition time of
the differential signal is EQUAL to the rise time of the individual signals
(400 ps for Scott's example). If one signal is skewed by the magnitude of
the rise time (400 ps), and the transition half-cycle (or data rate
half-cycle) is sufficiently long (~800 ps or greater), the differential
signal still achieves full 100% peak-to-peak amplitude, but exhibits a
degradation/doubling in rise time from 400 ps to 800 ps. Arbitrarily
assuming an 800 ps half-cycle, the width of the window would be reduced from
800 ps (ideal case) to 400 ps (no-crossover case) or 50% and the dwell time
at full amplitude would be reduced from 400 ps to 200 ps (in each
half-cycle), again a 50% reduction (only a coincidence). Note, however, that
if the data rate half-cycle is longer than 800 ps, the impact is reduced in
time on a 1:1 basis; i.e., stretching 800 ps to 1200 ps changes the
differential signal full-amplitude dwell time by (1200-800+200) ps = 600 ps,
which is three times the previous value. The rise time is of course still
800 ps for the cited no-crossover case.

As I see it, there is no direct eye pattern correlation in system
functionality (or malfunction) except on differential clock lines or in chips
operating at (or above) the clock frequency. Perhaps someone can cite
exceptions to this (perhaps ignorant) view.


Michael L. Conn
Owner/Principal Consultant
Mikon Consulting

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