RE: [SI-LIST] : Parallel Termination in Theory and Practice

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From: abe riazi ([email protected])
Date: Tue Aug 01 2000 - 11:03:31 PDT

Dear Chuck and Scott:

Thank you very much for your interesting replies.

Another important point related to topic of termination is appraisal of internal vs. external termination. The internal termination appears to offer advantages of eliminating the need for external stubs and components. But this is achieved at the price of sacrificing flexibility. For instance an IC having internal series termination eliminates the need for an external series resistor and the associated stub. But the disadvantage is that series termination is suitable only for certain routing topologies (such as point to point routing) and not the right for choice for other types of topologies (such as daisy-chain ). Similar reasoning applies to internal parallel termination. Variations in the characteristic impedance of the trace can be also better dealt with by use of external terminators.

What are your thoughts on this subject ?

Thanks again.

-----Original Message-----
From: Chuck Hill [SMTP:[email protected]]
Sent: Tuesday, August 01, 2000 6:19 AM
To: Scott McMorrow; abe riazi
Cc: '[email protected]'
Subject: Re: [SI-LIST] : Parallel Termination in Theory and Practice


Very good points from Scott. I'd like to add in regard to point #4 that
the stubs are also capacitively and inductively loaded. So the stubs can
resonate at frequencies far lower than the 1/4 or 1/2 wavelength value.
When these resonances are lower in frequency than the bit rate, they
contribute to pattern dependent jitter (as described in point #1).
Remember that two capacitively (or inductively) loaded stubs can resonate
together as the transmission line performs an impedance transformation.

"Critical length" is used as a decision criterion to separate a lumped
parameter circuit from a distributed parameter circuit model. Scott's
comments address the limitations due to dispersion, loss in the
transmission line. My comments raise the issue of distributed circuit
effects appearing much lower in frequency than would be expected with
oversimplified modeling.

Since there are many other considerations, I apply the critical length
approximation with great care.


At 01:32 AM 8/1/00 -0700, Scott McMorrow wrote:
>abe riazi wrote:
>> Scott:
>> The critical length Lc (rather than a specific frequency or rise
time) is often used as a yardstick for distinguishing lumped and
distributed circuit elements and for setting acceptable limits on stub
>> Does concept of critical length break down at frequencies above 1GHz?
>Critical length is an interesting approximation. The evaluation of what
>is "critical" depends upon how much error can be tolerated in the
>result when one is using a lumped circuit approach over a distributed
>one. There is always error when using lumped circuits to model
>any sort of waveguide. For example, according to Christopoulous
>in "The Transmission-Line Modeling Method TLM", page 24, if
>lambda/10 is used as the size for lumped elements, there is
>still almost a 2% error in the propagation delay of the circuit over
>the true distributed circuit. The breakdown comes in the size of
>errors we can tolerate at high frequencies and the effects which
>are masked by oversimplified modeling.
>Several things happen with high frequency signaling:
>1) the period is reduced, increasing the chances of intersymbol
>interference occurring because of discontinuities in the line.
>(i.e. - ringing and jitter spill over into the next bit period.) This
>translates into less overall margin.
>2) the edge rate is increased to support the higher signaling rate
>which increases the bandwidth of the signals.
>3) the increased bandwidth of the signals causes a subsequent
>increase in sensitivity of the circuit to discontinuities.
>4) the increased bandwidth of the signals can excite stubs into
>operation at quarter wave resonances. ( large packages
>like BGA's make for very nice stubs with a large discontinuity
>at both ends. A capacitive discontinuity at the die and a
>Z to Z/2 mismatch at the pin breakout when the device is
>placed on a line terminated at the far end. This structure
>forms a very nice resonator if excited with a high edge rate
>source.) Hmmm ... I wonder what might happen at say ...
>400 MHz with 800 Mb/s signaling on a bus with a single
>parallel end terminator and one BGA driving another? This
>might form two resonant circuits ... one from device to
>device and the other from trace to package. Like this:
>BGA ----------------------------------terminator
> | (package resonance)
>|<- resonant circuit ->|
>5) these quarter wave resonant stubs can perturb signals
>causing excessive jitter.
>6) Multiple stubs on a single line with nearly similar resonant
>frequencies can form high frequency bandpass filters which
>actually amplify the resonances. This will greatly increase
>signal jitter and can cause high bit error rates which are
>pattern sensitive. (If multiple devices of the same type and
>package are daisy chained on a parallel terminated line
>then it is most likely that the package interconnects have
>nearly the same resonant frequency. This greatly increases
>the chances of something bad happening.)
>7) Resonant points of all circuits involved can change
>due to even and odd mode coupling to neighboring circuits.
>This makes it even more interesting to diagnose and track in
>operating systems.
>8) Unbalanced data coding as used in most computer systems
>will cause large average DC level variations dependent upon the
>data pattern being transmitted. These DC level variations
>translate into decreased eye margin for differential signals
>and increased timing jitter (skew) for non differential signals.
>9) A capacitor is not just a capacitor any more ... and this
>includes die capacitance. Since all include some physical
>length of interconnect to get to the capacitance there is a
>delay and an associated inductance. Ignore the inductance
>and the nifty little trace width impedance compensation circuit
>that you might design will not work so nicely.
>10) There are little capacitors everywhere ... especially in
>device pads and pad stacks. These little capacitors reflect
>quite a bit of "stuff" when hit with fast edges. Removing
>excessive capacitance in layouts removes a lot of excessive
>jitter ... which is just a by product of "stuff" reflecting.
>These are some of the interesting effects at high frequencies that
>can be easily ignored when moving up from SI engineering at lower
>frequencies. The guys who have experience doing RF and Microwave
>work have been used to these effects for years.
>A frequency domain sweep will uncover unwanted resonances
>quite nicely ... and help to better understand what is happening
>in the time domain. This is where transmission line simulators
>like XTK, SpectraQuest, ICX and Hyperlynx fall short. These can
>all do a good job of simulating in the time domain at high frequencies
>but can't perform simple AC sweeps. An AC sweep will often
>explain why a circuit won't perform beyond a particular frequency
>or why jitter can rise to unacceptable levels.
>This was a long winded answer to a simple question.
>I hope it helps.
>best regards,
>Scott McMorrow
>Principal Engineer
>SiQual, Signal Quality Engineering
>18735 SW Boones Ferry Road
>Tualatin, OR 97062-3090
>(503) 885-1231
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