RE: [SI-LIST] : inductance extracted by ansoft SI3D

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From: Hassan Ali ([email protected])
Date: Wed Jul 19 2000 - 07:46:20 PDT

Thank you very much for taking the time to explain to me the techniques in
via design/modeling. Dan Swanson kindly sent me more details of his novel
approach. He seems to follow that adage: "the best way to predict the future
is to create it". He designs the vias and optimize them to an extent that he
doesn't need to simulate the vias any more!
But Dan's approach can only be implemented when you have the luxury of
designing the via layout. In my situation, I have to characterize already
laid-out through-hole vias of a connector and in the connector field I
cannot put any more ground vias. All I have at my disposal is to play around
with the connector pinout to ensure that the signals (differential) would
work. In this case I have to know the parasitics of the vias to be able to
simulate the performance of each pinout.
I'd appreciate getting a copy of the paper by Dr. Henri Merkelo's student.
Do you know where I can get it from?
Someone suggested that I use IE3D, a field solver, to compute the
lumped-element equivalent circuit of my vias. Anyone with experience with
that tool? Is it accurate for high frequencies > 2.5 GHz?

Hassan Ali <[email protected]> 
Equipment & Network Interconnect, Nortel Networks 
2 Brewer Hunt Way, Kanata ON, K2K 2B5 Canada 
Tel: 613-765-1410 (ESN 395) Fax: 613-765-5512 (ESN 395) 

-----Original Message----- From: Jeff Walden [mailto:[email protected]] Sent: Monday, July 17, 2000 7:45 PM To: si-list Subject: RE: [SI-LIST] : inductance extracted by ansoft SI3D

Hassan, Is it more important to model a stackup like that & try to safely simplify the model, or could the structure be simplified ... electrically? Keep the layer stackup the way you want, but use the novel idea that Dan Swanson (of the RF persuasion) has used which is a 5 wire transmission line structured out of vias. The return loss can be easily adjusted to below 20dB over a broad frequency range (sort of a SI interest) ... albeit a loss of board space. Below is a feeble attempt describe the geometry. The G's are vias tying the ground planes together & S is the the signal via. Optimization is needed to adjust the spacing of the ground vias & possibly adjust the barrel diameter. To a point, the smaller the via barrels the smaller the radius of the Gs. G G S G G You will use a full wave field solver. Technically any will do, BUT a 3D planar will cut the run time down enormously, i.e. Sonnet EM (RF persuasion), it may at this time even have an optimization routine built in. The model then becomes a transmission line ... Zo & Td which is pretty simple. I would estimate solver run time on the order of several minutes to a couple of hours + curiosity = a few days to a solution. Alternatively, one of Dr. Henri Merkelo's (SI persuasion) students published a paper a few years ago in which he meticulously modeled a via through 3 ground/power layers. I think it was presented at ECTC ~'93 or '94. With his SPICE model he even successfully represented the mode conversion between the layers with controlled current source(s). Their tool was a full wave time domain field solver, written at the U of I, that could also generate a time transient animation of the charge propagation. (Great visualization for those of the SI persuasion.) I know of at least 2 commercial full wave time domain field solvers that can replicate that effort, i.e. Micro-Stripes from Flomerics & Microwave Studio from CST. With enough "probes" between layers, near adjacent vias & traces you should be able to successfully capture most of the important effects ... albeit a loss of (your) time. I would estimate solver time in days + your time in days = weeks. -JLW

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