**From:** Muranyi, Arpad (*[email protected]*)

**Date:** Mon Jul 17 2000 - 14:22:13 PDT

**Next message:**Hassan Ali: "RE: [SI-LIST] : inductance extracted by ansoft SI3D"**Previous message:**Chris Cheng: "RE: [SI-LIST] : inductance extracted by ansoft SI3D"**Maybe in reply to:**Ming: "[SI-LIST] : inductance extracted by ansoft SI3D"**Next in thread:**Dima Smolyansky: "Re: [SI-LIST] : inductance extracted by ansoft SI3D"**Reply:**Dima Smolyansky: "Re: [SI-LIST] : inductance extracted by ansoft SI3D"

There is one thing that doesn't get mentioned in this discussion.

Even if your TDR head is capable of 35 ps, which corresponds to

something between 1-2 mm, the problem is that by the time this

signal from the TDR head gets to the via of interest, the rise

time will be much less due to losses and dispersion in the path

to the via. So chances are that you may not see it at all...

Another thing I would like to mention is that I am not aware of

any techniques that can give you the loss parameters from a TDR

measurement. Transmission line models can't be modeled without

the losses accurately any more.

Arpad Muranyi

Intel Corporation

================================================================

-----Original Message-----

From: Dima Smolyansky [mailto:[email protected]]

Sent: Monday, July 17, 2000 11:45 AM

To: si-list

Subject: Re: [SI-LIST] : inductance extracted by ansoft SI3D

Matt:

TDR's typical resolution is, in fact 1-2mm, assuming reflected rise time of

25-40ps. If you try and TDR your tiny package via, you probably will see a

very small blip (dip?), which you could probably correlate to some

capacitive / inductive value, but with moderate accuracy.

However, if a 35 ps TDR does not see an element, one probably needs to ask

him/herself a question: What is the rise times of the actual signals

propagating through that package, and will these signals see this tiny

discontinuity? As you know, for slower rise times, the capacitive/inductive

discontinuities become even less visible to the signals propagating through

it, and if your driver rise time is 100ps, you won't see the tiny via at

all.

Thanks,

===================

Dima Smolyansky

TDA Systems, Inc.

11140 SW Barbur Blvd., Suite 100

Portland, OR 97219

(503) 246-2272

(503) 246-2282 (fax)

(503) 804-7171 (mobile)

http://www.tdasystems.com <http://www.tdasystems.com>

The Interconnect Modeling Company(TM)

----- Original Message -----

From: Matt <mailto:[email protected]> Kaufmann

To: si-list <mailto:[email protected]>

Sent: Monday, July 17, 2000 10:12 AM

Subject: RE: [SI-LIST] : inductance extracted by ansoft SI3D

Does TDR have enough resolution to isolate the effects of a single package

via (maybe only 0.1-0.3mm long) from other elements (traces, other vias) in

the package? My understanding is that TDR resolution is on the order of 1-2

mm (after converting time to distance).

Matt

-----Original Message-----

From: [email protected]

<mailto:[email protected]>

[mailto:[email protected]]On Behalf Of Dima Smolyansky

Sent: Monday, July 17, 2000 9:35 AM

To: si-list

Subject: Re: [SI-LIST] : inductance extracted by ansoft SI3D

Hello:

There is always, of course, the way of the TDR.

If the via is so long compared to system rise time that it needs to be

considered a distributed elements, TDR extracts the Z and Td quite nicely.

If it is necessary to compute L and C of the via separately, extending the

JEDEC publication JEP-123 from packages to other elements, one can do it, as

long as one is able to create appropriate test structures beforehand. R is a

separate issue, but R is typically a small number, millohm one hopes, is it

not? In that case, it is best measured with a DC meter, which can provide an

accurate value.

There are also TDR techniques for computing partial or loop inductance

values, depending which is required.

Thanks,

===================

Dima Smolyansky

TDA Systems, Inc.

11140 SW Barbur Blvd., Suite 100

Portland, OR 97219

(503) 246-2272

(503) 246-2282 (fax)

(503) 804-7171 (mobile)

http://www.tdasystems.com <http://www.tdasystems.com>

The Interconnect Modeling Company(TM)

----- Original Message -----

From: Hassan Ali <mailto:[email protected]>

To: si-list <mailto:[email protected]>

Sent: Monday, July 17, 2000 7:47 AM

Subject: RE: [SI-LIST] : inductance extracted by ansoft SI3D

*> > 2.For a via through several power and ground planes, does the SI 3D
*

*> > consider the effects of those planes when doing the extraction?
*

*> >
*

*>
*

*> For this I believe you need a full wave solver such as their HFSS. Edge
*

*> rate (frequency content) & geometry really are the factors. If you edge
*

*> rate is slow compared to the geometry, then the complication of an
*

*> additional solver MAY not be necessary. But, since we MAY not know all
*

*> those rules of thumb & guidelines, take no chances & use a full wave
*

because

*> you probably do have edge rates which are "fast". Your investment in
*

*> understanding a refined full wave solver will be worth it.
*

As to the original question, AFAIK (as far as I know) Ansoft SI Q3D is NOT

capable of computing via parasitics in consideration to individual planes.

You see, SI Q3D considers the entire via structure comprising of the signal

traces connected to the via, the via barrel (the plating on the via hole),

and all the pads at different layers, as ONE conductor. ALL the ground

planes are considered connected hence they make ONE conductor. In that case,

the self L and R values computed for the via structure are for the ENTIRE

via structure as mentioned above (i.e. not just for the via barrel), and the

capacitance to ground is with reference to ALL the ground planes (i.e. you

don't get separate values for capacitance with reference to EACH individual

ground plane). That information is not very useful for critical SI analysis.

And unfortunately, I don't know of any software tool that can accurately

compute separate parasitics. Any suggestions?

To illustrate further the problem in question, suppose I want to include via

parasitics for a signal that goes from the top pcb layer to an inner signal

layer, then I need to include via parasitics of only that portion of the via

that gets into the path of my signal i.e. not the parasitics of the entire

via structure. Any body knows how to do that with the presently available

tools?

As to the capabilities of HFSS, I think many people make wrong assumptions

on how full-wave field solvers can help us (SI engineers). First of all HFSS

would NOT spit out via parasitics! Using your various signal traces as

"ports", HFSS can accurately compute scattering (S) parameter matrix for all

the ports. These S-parameters are computed for each propagation mode of

interest (e.g. TEM mode) and indeed takes into account the electromagnetic

(EM) field interactions of all the structures in the geometry of the problem

(e.g. for a via, all the conductors, power and ground planes).

That is well and good, but the problem is that you CANNOT (easily) separate

individual interactions in terms of R, L, and C parasitics. The only method

I know of is to find a lumped-element equivalent circuit (which may not be

unique) and use a microwave circuit simulator (like Touchstone, Libra, ADS,

MDS, Ensemble, SuperCompact, APLAC, etc.) to optimize the R, L, and C,

values to make the equivalent circuit have the same S-parameters as the

original 3D structure. This is a painful process and at best not accurate

and reliable. This is because, at high frequencies, all the parasitics are

distributed and therefore cannot (easily) have an accurate lumped-element

equivalent. Am I too much of a pessimist here? Any ideas of what works best?

Regards.

Hassan.

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**Next message:**Hassan Ali: "RE: [SI-LIST] : inductance extracted by ansoft SI3D"**Previous message:**Chris Cheng: "RE: [SI-LIST] : inductance extracted by ansoft SI3D"**Maybe in reply to:**Ming: "[SI-LIST] : inductance extracted by ansoft SI3D"**Next in thread:**Dima Smolyansky: "Re: [SI-LIST] : inductance extracted by ansoft SI3D"**Reply:**Dima Smolyansky: "Re: [SI-LIST] : inductance extracted by ansoft SI3D"

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