From: George Borkowicz ([email protected])
Date: Thu Jun 15 2000 - 11:57:25 PDT
Arnold, Arpad and Donald
Thanks a million for your comments. Thus, 5, 10 & 15 it shall be and my
model is ready. Besides initial PCI guestimates it is actually fun to use
simulator comparison ( given such primitive specification model). Thanks
> -----Original Message-----
> From: Donald Telian [SMTP:[email protected]]
> Sent: Monday, June 12, 2000 4:08 PM
> To: Borkowicz, George [KAN:0M21:EXCH]; Muranyi, Arpad
> Cc: '[email protected]'
> Subject: RE: [SI-LIST] : PCI clamp spec
> The spec was derived by:
> 1) sweeping the clamp stregth on the original "speedway" implementation
> (and a couple other topologies) to see where it breaks
> 2) for certain positions on the bus, it would break for a resistance
> somewhat higher than 15 Ohms
> 3) 15 Ohms was proposed, as a reasonably guardbanded number
> 4) 15 Ohms was verified as achievable (with quite a bit of margin even) by
> every device that we could either get a good model for or sweep on a curve
> tracer. That included almost every ASIC line available at the time (that
> was late 1991, and 1.2u was common). I'd also add that curve tracing was
> much more reliable than models back then as far as clamp characteristics
> were concerned.
> 5) Extensive "robustness" Monte Carlo runs were then performed to
> challenge this and other determined specs.
> 6) Test boards and ASICs were built to verify this all again empirically.
> 7) Specs were published, and then real boards/chips were built.
> So I think what you are doing now is constructing a "typ" or "max" model
> of a PCI buffer and wondering what a reasonable value for the diode on
> resistance would be? If so, I think that most clamps (again, circa 1992)
> were in the 5 Ohm region. You might use 5 for max and 10 for typ. Arpad
> would still have access to the orignal plots and overlays, and could
> verify this (if he's up for it) - I left all that at Intel when I left.
> Naturally these numbers are not "specs" (and never will be), but I think
> you were asking for best guess anyhow.
> Donald T.
> At 11:36 AM 06/12/2000 -0700, Muranyi, Arpad wrote:
> Since my name was mentioned I feel I have to respond.
> The original PCI spec (mentioned in the mail below)
> had only one clamp definition because the intension
> was to spec the minimum required(?) clamping.
> Anything stronger was thought to be better.
> If it can be proven that the spec is broken with these
> clamps and stronger drivers which are still within the
> spec's limitations the spec needs to be corrected.
> Just a word of caution, buffer designers do not like
> the idea of relying on the clamps for signal integrity
> purposes, unless the clamps are specifically designed to
> do that. So it may be a better idea to avoid overly
> strong buffers.
> Arpad Muranyi
> Intel Corporation
> -----Original Message-----
> From: George Borkowicz [mailto:[email protected]]
> Sent: Monday, June 12, 2000 7:02 AM
> To: '[email protected]'
> Subject: [SI-LIST] : PCI clamp spec
> Hi everybody.
> Long before you and me and IBIS Intel (Arpad Muranyi I believe) came
> with the behavioral model of the 5V PCI spec. To these days the
> model and
> the template are included as a sample in HSpice suite. Well, now
> HSpice supports IBIS (for better or worse) and other people here do
> use HSpice it seemed a good idea to recreate this effort in IBIS.
> so was done.
> Now the issue. All flavors of PCI spec seem to specify one minimum
> clamp limit roughly as a 15 ohm resistor offset by .625 V. This size
> is supposed to fit all (weak and strong). It probably does so on
> short, slotted buses ("speedway" they were called) but not so on the
> long stub-less runs which happen to be the reality of clusters of
> ASICs and multi-board systems("subway" was the name). If one
> such a clamp with anything but the weakest driver one usually ends
> with the broken bus. To damp the reflections, systems with strong
> must rely on the clamps to do the job. So to be realistic, in the
> spec model
> I need to associate stronger clamps with strong (and typical)
> Short of using an ideal diode does anyone has an idea what would
> be a good resistance number here?
> George Borkowicz
> Nortel Networks
> Donald Telian
> PCB Systems Division
> Cadence Design Systems
> phone: 408-944-7791
> [email protected]
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