Re: [SI-LIST] : pcb plane cap and mixed bypass cap value....

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From: Larry Smith ([email protected])
Date: Tue Jun 13 2000 - 13:18:41 PDT

Chris - you have some good comments below. One particularly important
concept is dividing up decoupling into two areas: core and IO. They
are very different beasts.

Core power tends to be higher than IO power (50 core watts compared to
less than 5 IO watts for some processors). The lumped inductance for
the core package mounted on power planes is likely to be 100 pH. That
inductance limits the current that goes in or out of the package at a
given frequency:

        frequency impedance of 100 pH
        --------- -------------------
         10 MHz 6.28 mOhm
         30 MHz 18.8 mOhm
        100 MHz 62.8 mOhm
        300 MHz 188 mOhm
          1 GHz 620 mOhm

One could argue that there is no point in having a PCB power plane
impedance significantly less than the above table. The on-chip
capacitance must satisfy the current needs of the circuits because the
package inductance stands between the circuits and the PCB. As we
drive the mounted inductance of the uP core down, we will need to have
a corresponding reduction in PCB power plane impedance because the uP
core will be wanting to draw current from that low impedance.

Another reason to have low impedance on the core power planes is EMI.
Energy from the clock and clock harmonics are attenuated by the package
inductance but still make it out to the PCB. The PCB must be
sufficiently low in impedance at those frequencies to contain the EMI.

The IO circuitry does not draw as much power as core so the target
impedance is less, but the power planes must maintain the target
impedance to a much higher frequency. One half nSec edges have
frequency content to over 700 MHz (f=0.35/tRise).

For a microstrip line centered between a Vdd and Gnd plane, an equal
amount of return current is carried by the Vdd and Gnd plane,
regardless of the direction the signal switches or how it is hooked up
to a driver, receiver or termination. If the microstrip hits a via and
the signal moves to a new layer the return currents must be resolved.
Bounce on power planes is basically proportional to the return currents
and the impedance between the planes that carry the return currents.
In many cases, return currents must transfer from Vdd planes to Gnd

That is why low impedance is required between any power planes that
carry signal return currents. Edges will be distorted and timing and
eye diagrams will be affected if there is not sufficiently low
decoupling impedance between planes. This is especially important near
a uP or major ASIC that has many simultaneously switching IO.

Larry Smith
Sun Microsystems

> From: Chris Cheng <[email protected]>
> Cc: [email protected]
> Subject: [SI-LIST] : pcb plane cap and mixed bypass cap value....
> Date: Mon, 12 Jun 2000 19:06:50 -0700
> MIME-Version: 1.0
> there seems to be a lot of discussions about using pcb capacitance
> or spreading bypass caps value for flat response. i would like to
> offer some counter points to the discussions.
> for core noise decoupling
> in all of my analysis for core power decoupling, whether using wire
> bond or c4 packages, the package inductance (bond wire or c4 bump/
> distribution, core via and package pin) is so high that no external
> decoupling can help or contribute to the initial transient. you
> can connect an ideal source to the pin and it still won't help
> the initial transient voltage drop. it seems to me other than
> on die decoupling and on package decoupling capacitors, any
> attempt to use external decoupling caps for >500MHz core noise
> is not effective.
> if you buy into the above observation, the function of external
> caps are only used for resupply the depleted charges of the
> on die or package decoupling caps. a mere few hundred pf from
> the plane capacitance is not going to cut it. what you really
> need is the bulkiest and lowest esl/esr cap you can place and
> manufacture near your package. followed by even larger and
> bulky cap further away until the power supply wakes up. i
> have not seen any benefit from caps that is lower than 0.01uf
> in suppressing core noise at all. think about it in another way,
> if external decoupling can do the magic, why does sso happens ?
> hint, the package inductance gets in the way.
> for i/o noise decoupling
> i believe its is more important to have tight coupling between
> the signal traces and the power/ground return plane for its
> return current NOT tight coupling between the power and ground
> plane. remember, i/o current flow from power through the signal
> trace or from signal trace to ground return NOT between i/o power
> and ground plane.
> if you buy into the above, for a finite number of layer stack
> up in pcb, it makes more sense to sandwich the signals between
> the power/gnd plane than pairing up the power plane and leave
> the signals to dual strip layers.
> as for the 1/4 wavelength placement etc. what you need to
> realize is that by the time the noise goes through the package,
> it is no longer a high speed single point source but rather a
> lower speed drupe spread out across the package. 1/4 wavelength
> and distance is meaningless given the size of the package.
> chris
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