From: Muranyi, Arpad ([email protected])
Date: Mon Jun 12 2000 - 11:36:52 PDT
Since my name was mentioned I feel I have to respond.
The original PCI spec (mentioned in the mail below)
had only one clamp definition because the intension
was to spec the minimum required(?) clamping.
Anything stronger was thought to be better.
If it can be proven that the spec is broken with these
clamps and stronger drivers which are still within the
spec's limitations the spec needs to be corrected.
Just a word of caution, buffer designers do not like
the idea of relying on the clamps for signal integrity
purposes, unless the clamps are specifically designed to
do that. So it may be a better idea to avoid overly
From: George Borkowicz [mailto:[email protected]]
Sent: Monday, June 12, 2000 7:02 AM
To: '[email protected]'
Subject: [SI-LIST] : PCI clamp spec
Long before you and me and IBIS Intel (Arpad Muranyi I believe) came up
with the behavioral model of the 5V PCI spec. To these days the model and
the template are included as a sample in HSpice suite. Well, now that
HSpice supports IBIS (for better or worse) and other people here do not
use HSpice it seemed a good idea to recreate this effort in IBIS. And
so was done.
Now the issue. All flavors of PCI spec seem to specify one minimum
clamp limit roughly as a 15 ohm resistor offset by .625 V. This size
is supposed to fit all (weak and strong). It probably does so on the
short, slotted buses ("speedway" they were called) but not so on the
long stub-less runs which happen to be the reality of clusters of large
ASICs and multi-board systems("subway" was the name). If one applies
such a clamp with anything but the weakest driver one usually ends up
with the broken bus. To damp the reflections, systems with strong drivers
must rely on the clamps to do the job. So to be realistic, in the spec
I need to associate stronger clamps with strong (and typical) buffer.
Short of using an ideal diode does anyone has an idea what would
be a good resistance number here?
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