Re: [SI-LIST] : Current handling capability of etch......

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From: Doug McKean ([email protected])
Date: Mon Jun 12 2000 - 11:25:02 PDT


If you're anticipating standard printed circuit board
procedures, I recommend the IPC specs. They are the
industry standard for boards for not only domestic but
on an international level.

Specifically, IPC-2221, Feb 1998 (which supercedes
IPC-D-275, Sept 1991), Figure 6-4, pg. 38.

If you could provide if the trace is going to be an
external layer or internal layer trace and the degree
rise allowed (sorry these really are needed), I could
give more of an answer.

Otherwise, the tables show the two traces you cite as
(this is tough for the specs you gave are at the far
 end of the tables where the graphs all come together,
 the 1.5 oz is not on the tables and I'm doing this
 by eye ...)

External Layer Trace Current (degree C rise)
                               10C 20C
-------------------- --------------------------
 1/2 oz 4 mil wide ~ 0.25 Amps ~0.325 Amps
 1.5 oz 6 mil wide ~ 0.5 Amps ~0.625 Amps

Internal Layer Trace
-------------------- --------------------------
 1/2 oz 4 mil wide ~ 0.125 Amps ~0.25 Amps
 1.5 oz 6 mil wide ~ 0.25 Amps ~0.37 Amps

You can get these specs from the IPC website at

The data in the tables was gathered from extensive
empirical testing.

Regards, Doug McKean

"Greim, Michael" wrote:
> Hi Everyone,
> Does any of you have a good reference or set of equations
> regarding the current handling capability of etch. I am
> interested in absolute maximum as well as good design
> practice ratings. I have some devices that have wired powers
> and while the frequency requirements are low, I am con-
> cerned about current handling capability. The two pieces
> of etch that I am concerned about is a half oz. 4 mil wide
> etch and 1.5 oz 6 mil wide etch.
> Thanks in advance for the assistance.
> Best Regards,
> Michael Greim

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