From: Greim, Michael ([email protected])
Date: Thu May 25 2000 - 09:39:03 PDT
> I'm designing a board that has to fan-out a 150MHz LVDS clock
> to 5 destinations (4 connectors and 1 IC). Because the 4
> connectors may have cables connected to them, I want to run
> each clock line point-to-point. To my surprise, I cannot find
> a 1:5 LVDS clock distribution IC like they have for TTL (maybe
> someone knows of one, hint-hint).
[Greim, Michael]
National has something that is either out or will be shortly.
Talk to them about the details.
> My question is, what problems will I have if I run the input
> clock to 5 receivers of an 8 port LVDS repeater (assuming the
> repeater meets my skew requirements)? That would mean there
> would be 5 loads on the incoming clock line, but the loads
> would be very close together since they are in the same
> package. How would I terminate this (as in, where would I
> place the 100ohm resistor?) Should I just daisy-chain the
> clock to the 5 inputs, then place the resistor at the end of
> the line?
[Greim, Michael]
This sounds not dis-similar to existing BLVDS applications.
TI and National have design guides for this type of thing. The
problem as I see it is what is your skew budget and can this
type of implementation hit your numbers. I believe that you
could put together a scheme electrically that would hang
together.
> I should mention that I will have an Altera APEX FPGA on the
> board that can handle LVDS I/O's. If I have enough spares, I
> wonder if I could use the FPGA to fanout the clocks, or is
> this not considered good practice?
[Greim, Michael]
Depends on what your skew requirements are. If your skew
requirements are not too bad, this might not be a bad alternative.
> Unforunately I don't have much information on the incoming
> clock driver. I know it can come from one of 2 sources,
> either an offboard source over a cable or an onboard IC.
>
> Thank you very much,
>
> Chris
>
>
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