[SI-LIST] : Fanning out an LVDS Clock

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From: Chris Bobek ([email protected])
Date: Wed May 24 2000 - 13:52:51 PDT


I'm designing a board that has to fan-out a 150MHz LVDS clock
to 5 destinations (4 connectors and 1 IC). Because the 4
connectors may have cables connected to them, I want to run
each clock line point-to-point. To my surprise, I cannot find
a 1:5 LVDS clock distribution IC like they have for TTL (maybe
someone knows of one, hint-hint).

My question is, what problems will I have if I run the input
clock to 5 receivers of an 8 port LVDS repeater (assuming the
repeater meets my skew requirements)? That would mean there
would be 5 loads on the incoming clock line, but the loads
would be very close together since they are in the same
package. How would I terminate this (as in, where would I
place the 100ohm resistor?) Should I just daisy-chain the
clock to the 5 inputs, then place the resistor at the end of
the line?

I should mention that I will have an Altera APEX FPGA on the
board that can handle LVDS I/O's. If I have enough spares, I
wonder if I could use the FPGA to fanout the clocks, or is
this not considered good practice?

Unforunately I don't have much information on the incoming
clock driver. I know it can come from one of 2 sources,
either an offboard source over a cable or an onboard IC.

Thank you very much,


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