RE: [SI-LIST] : SI simulation issue for open-drain device

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From: ARNOLD,PETER (HP-Cupertino,ex3) ([email protected])
Date: Wed May 24 2000 - 09:29:04 PDT


1) AGTL+ ("Assisted" Gunning Transceiver Logic) in fact has an active PMOS
device pulling up as the output transitions from Low->High state. This
device turns off after a few nanoseconds and the output reverts to open
drain configuration.

2) Here is how I think about the overshoot seen at the driver on open-drain
L->H transitions. Consider a driver pulling a long o/d line low. After
everything settles, a standing current is flowing from the net's pullup
resistor(s), through the driver's source resistance and then to ground. Now
imagine that driver turns off instantaneously. The current keeps coming from
the net but cannot go through the FET any more so is reflected back the way
it came, into the transmission line. This results in a voltage V = I x Z0
added to the existing low-level voltage that was on the line before. For a
50 ohm net with 25 ohm pullup and a driver source resistance of 12 ohms, the
added pulse would reach over 2V as about 40mA of steady-state current
reflects back into the 50-ohm line.

Of course the driver doesn't turn off instantly in real life and there may
be clamping so the effect is mitigated. Adding a PMOS pullup FET as in AGTL+
serves to lower the reflection, since the initial "off" condition at the
driver becomes not an open-circuit but some low resistance to 1.5V. This
lowers the reflection coefficient from +1 closer to 0, but it doesn't cut in
right away (see driver-schedule activation delay.)

Try commenting any clamp diodes out of the model. They may not be effective
on short time-scales.

peter arnold.

-----Original Message-----
From: [email protected] [mailto:[email protected]]
Sent: Tuesday, May 23, 2000 10:29 PM
To: [email protected]
Cc: Peng, Smith (???)
Subject: [SI-LIST] : SI simulation issue for open-drain device
Importance: High

Dear SI gurus:
     Recently, we found one very strange, but interesting thing, i.e. we
used some open-drain devices for AGTL+ signal integrity simulation, but we
got such surprising phenomena between simulation and measurement. So here,
we'd like to ask your great help to clarify and solve our questions on
open-drain feature (Please see my below questions in detail.), and how to
define its IBIS model exactly and properly.
(1) From our understanding about open-drain concept, it's in high-Z stage
for P-MOS when L->H transition, meanwhile, it also uses pull-up voltage to
drive out. My question is does it really stay "High-Z" stage and no current
go through its "power-clamp" diode??
(2) From our measurement result, we get an obvious rignback after rising
edge for open-drain device. But we don't get this from our simulation tool.
So we check our open-drain model and find that it defines "L->H" V/I curve
for P-MOS, not using "High-Z" definition. So we modify it as "High-Z"
condition and obtain the similar result to measurement after re-simulating.
We also check Intel's models, such as CPU model which also defines "L->H"
V/I curve for P-MOS. Do you think which one is right, the "High-Z" or
existing "L->H" V/I curve for P-MOS?? Why?? Does any one know why the IBIS
model defines the "L->H" V/I curve instead of "High-Z" for open-drain device
with "Driver Schedule" keyword, at least Intel did it in their models.
(PS. Intel uses "Driver Schedule" keyword in IBIS model in order to let
P-MOS turn on/off by a little bit timing delay. But I don't understand why
its P-MOS has V/I curve for "Driver Schedule", but "High-Z" for general
open-drain definition??)
Best regards
Smith Peng
Email: [email protected]
Tel: 886-3-3900000 ext. 2152

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