From: Derek Tsai ([email protected])
Date: Tue May 23 2000 - 09:49:15 PDT
Please send all inquiries and resumes to
Sun Microsystems in Burlington, MA has an opening for an Electrical
Design and Signal Integrity Engineer to report into the Workgroup
DESCRIPTION OF RESPONSIBILITIES
Individual contributor responsible for the electrical performance of
the next generation SPARC system ASICs. Candidate will collaborate
with advanced packaging, cell and system design teams to develop ASIC
solutions that optimize chip/board/system performance.
PURPOSE OF POSITION:
Develop and implement processes and strategies to ensure high
performance system ASIC designs.
Engineer shall contribute to all aspects of the electrical
specification and performance of a complex ASIC including:
* refine/define the signaling architecture, signal quality/ integrity
criteria and package electrical requirements/goals.
* specify/design/model IO pads (in collaboration with ASIC vendor)
* chip-level timing strategies/analysis: clock tree design/analysis;
critical path analysis; pll specification/analysis;
spice/motive/vendor model correlation.
* external timing analysis: chip to chip and system level timing
analysis (incorporating I/O buffers, package and board topology)
* package development: evaluate/define/analyze pkg electrical
Must be able to summarize results of analysis in clear, concise fashion
and be capable of identifying and recommending tradeoffs and solutions
to technical issues.
THE FOLLOWING KNOWLEDGE AND SKILLS ARE TYPICALLY ACQUIRED THROUGH:
Typical numbers of years of relevant experience: 8+
Minimum level of education: BSEE required, MSEE preferred
Fields of study: EE/CE
Additional specialized coursework: Computer Engineering/VLSI
Would you consider recent college grads? No
REQUIRED KNOWLEDGE AND SKILLS:
Unix workstation-based tools/environment, UNIX shells/scripts/utilities.
Candidate must have solid practical and theoretical background with
emphasis on CMOS circuit design/modeling, CMOS IO buffer
CMOS clock distribution strategies/analysis, signal integrity,
line analysis, electrical performance of high speed busses (150Mhz+) and
IC package design and modeling.
PREFERRED KNOWLEDGE AND SKILLS:
Experience collaborating with package vendors in the design of high
performance/density packaging and with ASIC vendors in the development
of high speed drivers and/or custom cells is highly desirable.
Familiarity with signal integrity tools (HSPICE, Maxwell, Custom, Ansoft
2D/3D) ASIC physical design (floorplanning, clock distribution, timing
optimization, critical path analysis) and Cadence board design
environment (SpectraQuest) is highly desirable.
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