From: Earl Morse ([email protected])
Date: Mon May 22 2000 - 10:38:57 PDT
Brad,
Splits in layer 6 will have no effect on your traces since none
will be referenced to them. You already have a lot of interplane
capacitance since the power planes are already sandwiched between
ground. Reducing the thickness of the dielectric is another way to
increase that interplane capacitance. That may disturb the
characteristic Z of the traces you route in layer 6. Trading off the
interlayer capacitance for more routing space may be a good swap.
What are the frequencies involved on this board?
Barry,
How do I get on the SI-LIST?
Earl Morse
Portable Division EMC Design
Compaq Computer Corporation
Phone: 281.927.3607
Pager: 713.717.0824
Fax: 281.927.3654
Email: [email protected]
Emissions Control Laboratory
10320 Rodgers Road, EC106
Houst, TX 77070
-----Original Message-----
From: Barry Ma [mailto:[email protected]]
Sent: Friday, May 19, 2000 7:27 PM
To: [email protected]
Cc: [email protected]
Subject: re: Split Plane
Brad,
Here is my two cents worth:
Did you consider exchanging 7 and 8 for more capacitance between 5V and
gnd
planes? Suppose you have 10 mil or less plane spacing. I understand
that
you want to use a gnd plane as return plane for signals on layer 9. But
it's
OK to use 3.3V plane as return plane. The plane cap would work well to
let
return signals go from 3.3V plane back to gnd pins on layer 9.
It's also OK using part of 5V plane as additional 3V area. You'd better
stitch up the gap.
Regards,
Barry Ma
[email protected]
-------------
From: "Brad Crowell" <[email protected]>, on 5/19/00 2:04 PM:
I have been lurking in the shadows of the SI list for some time now, but
have come across a situation that I could use some advice on:
I am working on a board design that is using the following stackup:
1 - SIGNAL
2 - GROUND
3 - SIGNAL
4 - SIGNAL
5 - GROUND
6 - 5V PLANE
7 - 3.3V PLANE
8 - GROUND
9 - SIGNAL
10- SIGNAL
11- GROUND
12- SIGNAL
My problem is that we are running out of routing resources. Thus,
it has been suggested that a few traces could be routed on layer 6,
the 5v plane. The intent would be to route some traces for the 3.3v
devices which are located away from the 5v devices on the board. This
would reduce the effect of any splits in the plane. Also, since there
is a ground plane available as a reference for every signal layer,
a split in a supply plane shouldn't have much effect, if any. I am
inclined to think, with my limited SI experience, that this should
be ok, but would appreciate comments from some of the experts.
Thanks,
Brad
***************************************
Brad Crowell
Hardware Designer
AMIRIX Systems
***************************************
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