From: Ritchey Lee ([email protected])
Date: Fri May 19 2000 - 09:54:37 PDT
Differential signalling doesn't by definition, or any other rule, depend on
tight coupling for proper operation. Length matching is the only parameter that
really counts. Sure, you need to make sure that noise doesn't couple into the
pair differentially. Sid by side routing does not guarantee that on a PCB. On
the contrary, side by side routing in a PCB will aslways result in differential
noise coupling.
Common mode noise coupling only occurs when the field strength of the inducing
signal is the same in both wires. This cannot occur in a PCB when the inducer
is on the same layer as the pair.
Lee
Weston Beal wrote:
> Brian,
>
> By definition, differential signals should be tightly coupled. This implies
> close spacing. This does not necessarily mean that the seperation should be
> minimized. You need to do some analysis to decide the stackup, width, and
> space that creates the differential impedance that is correct for your
> design.
>
> Regards,
> Weston
>
> -----Original Message-----
> From: [email protected]
> [mailto:[email protected]]On Behalf Of Brian Seol
> Sent: Monday, May 15, 2000 9:38 AM
> To: [email protected]
> Subject: [SI-LIST] : Differential Clock Signal Pair
>
> Hi everyone,
>
> I have a simple question about trace layout design for a differential clock
> signal pair of high-speed CMOS memory packages. I have two design
> guidelines for that as follows:
>
> 1. SPACING between a differential clock signal trace pair must be
> MINIMIZED as well as matched in length in order to reduce noise.
>
> 2. Differential clock signal trace pair must be matched in length in order
> to achieve matched electrical characteristics, but SPACING between
> them must be MAXIMIZED in order to reduce crosstalk noise.
>
> Which do you prefer?
>
> Thanks and regards,
>
> Brian
>
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