[SI-LIST] : RE: Charge moving from decoupling capacitors

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From: George Tang ([email protected])
Date: Wed May 17 2000 - 12:41:13 PDT


As the speed of digital signals gets faster and faster, people begin
concerned with the distance for electric charge to move on power and
planes of multilayer PCB during the signal rise time from a decoupling
capacitor (cap) to a chip it serves. I would like to raise two

(1) The charge is moving in a metalic plane, not inside the dielectric
between pwr and gnd planes. Please let me know why you have to use the
propagation velocity in the dielectric, instead of that in the metal.

If you know the charge distribution and current density on the metal
you can solve for the E and H fields in the dielectric using the given
boundary conditions. What this shows is that the fields are generated
the moving charges on the plane and the moving charges on the plane are
induced by the fields as the fields strike the surface of the metal
This means the fields and charges must travel at the same velocity in
direction of propagation.

(2) The second question is regarding distance between the cap and the
Do we really have to limit the distance letting the charge have enough
to move from the cap to the chip during the rise time interval? I doubt

Take the running water system for example. When we open, then close the
water faucet within one second, does the water we've got in basin come
water tower (or water station, or reservoir)? No, it is the water that
resides in the pipe. As a matter of fact, we have a very large pipe -
pwr/gnd planes. Well, of cause you know, I did not mean we don't need
tower - the cap. ......

This is true if you have only DC current. For AC, you may have water in
pipe but no water out of the faucet if the faucet is switching out of
from the water in the pipe. For an IC that switches according to random
incoming data (meaning wide frequency range), you need to supply
instantaneous current for unspecified time duration, so there is no time
phase matching. To do that you need to reduce the source impedance by
minimizing the current path inductance. This can usually be done by
reducing the size of the current loop.

Barry Ma
[email protected]
Morgan Hill, CA 95037
Tel. 408-778-2000


George Tang

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