RE: [SI-LIST] : 20-H Rule and Self-Resonant Frequency of Power Pl anes

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From: Nadolny, Jim ([email protected])
Date: Wed Apr 19 2000 - 11:05:34 PDT

I agree with Mary.

I have worked as an EMI professional for the past 15 years and have
conducted some research with universities on EMI associated with backplane
connectors. This is not to say I can solve or totally understand every EMI
problem but I have been around this stuff for a while.

Now maybe I am off base here but I have always viewed the 20H rule as a
means to minimize the efficiency of a patch antenna. The electric field
between Vcc and ground at resonance looks dipole-ish and can be a low
efficiency patch. This was always the justification for stitching the edge
of PCBs with vias or edge plating. I am not saying that the 20H rule works
to decrease the efficiency of the radiating structure, I just figured this
would be the base analysis approach.

This deal with altering the transmission line resonance, I don't know. It
seems to me that the parallel plate transmission line (Vcc & gnd) is
terminated with an open whether you follow the 20H rule or not.

Lastly, if one can't describe an effect succinctly it typically is not very
well understood.

Jim Nadolny

-----Original Message-----
From: Mary [mailto:[email protected]]
Sent: Wednesday, April 19, 2000 12:45 PM
To: [email protected]
Subject: [SI-LIST] : 20-H Rule and Self-Resonant Frequency of Power

I am a "degreed engineer", but this explanation doesn't make sense to
me. Is
 Mark saying that a small change in the size of the power plane can
shift the
 power bus resonances by a factor of 2 or 3? What are flux-phase-skews?
> -----Original Message----- From: Scott McMorrow
> [mailto:[email protected]] Sent: Thursday, April 13, 2000 12:48 PM
> [email protected] Subject: Re: [SI-LIST] : 20-H Rule and
> Self-Resonant Frequency of Power Planes
> ...
> My book that you refer to, has a target audience of PCB designers, and
> "non-EMC" engineers (refer to Pages 1 and 2), and was NOT written for
> engineers or for those involved in advanced aspects of system design and
> signal integrity analysis (i.e., users of this reflector). This is a
> one encounters when writing a book - the target audience. Those on si-list
> would benefit more from my second book, "EMC and the PCB - Design, Theory
> Layout Made Simple." This book targets experienced engineers, and contains
> solid EMC theory and analysis. This new book is not appropriate for the
> audience of PCB Design Techniques for EMC Compliance. Because of the
> audience, in which the Introduction "clearly" identifies, I did not
> sophisticated details on a complex topic such as 20-H. With this email, I
> will now provide brief details on why this design technique works.
> The "self-resonance situation," noted in the statement within my
> to reflection and flux-phase-skews that reactive terminations present at
> end of a transmission line, if proper termination is not provided. Power
> ground planes are in reality transmission lines, and must be treated as
> such.
> Using a typical inductive model of approximately 3 nanoHenries/square
> centimeter that both ground/power planes can exhibit (because the chemical
> etching for laminate bonding can exceed one skin depth in copper), the
> "surface area" of the board may be extensively larger than it would appear
> from mechanical dimensions. This is in conjunction with a second order
> of interplane capacitance between the power and ground planes. Interplane
> capacitance can exhibit as much as a 10:1 variance, depending on the
> dielectric constant, physical size of the planes, and distance separation.
> The self-resonant frequency (SRF) of a capacitor is based on both
> and capacitive characteristics inherent within its structure. One tends to
> forget that the power and ground planes must be considered separate from
> discrete capacitors for this analysis. Discrete capacitors scattered
> throughout the assembly allows for a distributed effect to be observed
> both poles and zeros when combined with the power and ground plane
> The use of discrete decoupling capacitors has no effect on how and why the
> 20-H rule works, which is where past discussion on self-resonance
> this issue has occurred on the reflector, and why that analysis is totally
> wrong!
> Assume that a larger size PCB with a large edge area, (greater than
> square inches around the perimeter) is NOT terminated by components or
> utilized by devices and loads. The reflection time constant from the
> reflected electromagnetic wave from all edges of the board, reflected
> simultaneously back to the source driver, may indeed bring the overall
> parallel-plane SRF down to the frequency range of 200 to 400 MHz. Because
> all PCBs are square, the reflected wave hits the edge boundary of the PCB,
> observes an edge boundary discontinuity, and reflects back into the PCB
> structure. Depending on whether the wave front is coming or going, EMI may
> occur if termination is not provided for the transmission line, with some
> energy radiating off the edge of the board into free space or energizing a
> cavity structure. Multiply this effect with hundreds of device pins
> asynchronous, each with a reflected wave that propagates radially from the
> source driver, each with a reflection. This is the primary reason why it
> difficult, if not nearly impossible to simulate 20-H for a fully populated
> assembly. This is an EMI (electromagnetic field ) issue requiring
> domain analysis, and cannot be solve using SPICE or derivations of this
> simulation tool. One must examine 20-H with "many" component active, not
> one stimulation source. This is a primary reason why simulation of 20-H
> the time domain is not easily achieved.
> The purpose for undercut of the voltage plane by a physical dimension
> 20-H), is to remove an un-terminated stub caused primarily by unterminated
> planes. For this scenario, substitute the words "transmission line" for
> planes. When doing so, the concept becomes easier to visualize. When this
> perimeter "stub" is sufficiently large, based on the physical dimensions
> the board and the source current relative to the edge of the PCB, the SRF
> effects of the board can be dramatically significant to the detriment of
> power plane performance, hence EMI emissions. By undercutting the plane to
> the point of the last termination(s) that circumscribe the devices that
> actually loads down the planes, the SRF performance of the board can be
> dramatically improved, and yes, by factors as much as 2 or 3, but that
> "assumes" that the initial board layout was sufficiently inappropriate to
> have resulted in the SRF dropping to low as 200 to 400 MHz, due to
> dimensions and stackup assignment.
> For a properly designed PCB, the SRF is extremely high. Edge termination
> effects and other design aspects, including use of discrete decoupling
> capacitors, lowers the SRF of the finished assembly to about 200-400 MHz.
> This occurs if the board is poorly designed. The 2 to 3 times multiple
> in my book brings up the SRF back to where it should be. Clearly, if a
> was "that" bad in SRF, then appropriate terminations of the planes WOULD
> increase the performance by 2 or 3 times multiple, but that is not just
> per se. Other factors must be included in the analysis. For boards that
> poorly designed, the 20-H dimension would have to be increased due to
> excessively large end stubs.
> The overall concept is so simple how can one not visualize it?
> The "20-H" rule, in this book, was not clearly stated to be the primary
> factor for the increase in SRF, and I have endured harsh criticism because
> that omission based on the target audience for the book. The 20-H rule, by
> itself, is highly effective in improving edge-effect terminations of
> boards, and it is incorrect to state that the 20-H rule, by itself, would
> cause the 2 to 3 times alteration, when the precursor condition is that
> planes be undercut to the point where they are load-terminated WITHOUT
> stubs.
> Printed Circuit Board Design Techniques for EMC Compliance - A Handbook
> Designers " has been 100% rewritten into a 2nd edition, and will be
> late May for purchase. This revised edition has a very detailed section
> restates the information above, adding this important component of
> that was omitted in the first edition, information for degreed engineers
> reading a book written for the non-degreed.
> In the original experiments of the 20-H concept, which is in fact only a
> plane-edge flux termination concept (to bring the planes topologically to
> point of the load currents for termination) the physical dimensions of a
> resistor was of a size that would result in an approximate "20-H"
> The omission concerning the stub-edge primary concept in my book was
> unfortunate for members of si-list, yet totally appropriate for thousands
> PCB designers world wide who make extensive use of this popular reference
> book without the need for theory or mathematical analysis.
> With this disclosure, I hope all questions and concerns have been answered
> and the debate regarding whether 20-H is valid or not can forever cease.
> is a valuable design technique that is required with certain designs. Not
> PCBs require use of 20-H. This is where one must understand what is to be
> accomplished, and how to implement this technique properly. In the past,
> fantastic hints were provided by other professionals on si-list that
> to my discussion above. The hints that have been presented allows one the
> opportunity to think this concept through and learn, which in turn makes
> better engineers. Apparently, there are still a large number of engineers
> that demand to be told everything, thus never achieving personal technical
> excellence for themselves and their careers, by blaming everyone and
> everything they can for things they do not understand, including me, with
> unprofessional comments in a professional forum.
> If additional knowledge is desired regarding 20-H, please refer to the 2nd
> edition of my new book soon to be released.
> --Mark Montrose--
> Author of two IEEE Press books
> Printed Circuit Board Design Techniques for EMC Compliance - A Handbook
> Designers and EMC and the Printed Circuit Board - Design, Theory and
> Made Simple.
> ...
> --
> Scott McMorrow
> Principal Engineer
> SiQual, Signal Quality Engineering
> 18735 SW Boones Ferry Road
> Tualatin, OR 97062-3090
> (503) 885-1231

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