Re: [SI-LIST] : on-chip decoupling capacitance

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From: Jan Vercammen ([email protected])
Date: Thu Apr 13 2000 - 04:01:18 PDT


with respect to your questions on power supply decoupling. Have a look at an
extreme example of power supply decoupling in large and complex systems in
the IBM Journal of R&D vol 43, no 5/6, 1999, IBM S/390 Server at
Look in the article by Katopis et al. MCM Technology and Design for the S/390 G5 systems. There is
an IBM article which details the small decoupling cells used in their designs, however, I cannot
find immediately. Anyway, the IBM Journal site is a very useful resource for information on
design and signal integrity. Check out previous publications too!

Note that this IBM design is an extreme case and does not translate into decoupling design encountered
in for example a PC motherboard. I have met one of the team members in a seminar were details of
IBM designs were discussed in very general terms. This kind of work takes tens of man-years to complete
and it is something that is not within reach of most engineering teams.

The on-chip decoupling can go from several nF to several hundreds of nF's. For example, for
most recent CPU's the on-chip capacitance is likely over 100nF, with an extreme case of the latest
Alpha risc chips with more than 1uF of local capacitance. This local capacitance is by means
of a smaller capacitor decopling chip that is stuck on top of the cpu chip and uses wire bonding
to connect to the cpu chip. You can find some details on on-chip decoupling in the IEEE journal of
Solid-State devices and in a limited number of books (Kluwer Academic).


Jan Vercammen

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