RE: [SI-LIST] : IBIS question regards [Falling Waveform] / [Rising Waveform].

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From: Chris Rokusek ([email protected])
Date: Tue Apr 11 2000 - 15:02:07 PDT

Merav,

> Is this kind of wave is "harmful" to the IBIS model users? should I omit
it,
> and leave only the [Rising Waveform] with resistor connected to ground ?

No. Not at all. In fact your driver must drive resistive loads into both
the +V and Ground (two Rising + two Falling) in order to model your device
properly exactly because of the N/P delay you noted.

Please refer the IBIS cookbook for more details on making "correct" models:

        http://www.eda.org/pub/ibis/wip/ckbkwfw3.doc

Chris Rokusek
Innoveda

> -----Original Message-----
> From: [email protected]
> [mailto:[email protected]]On Behalf Of Merav Kass
> Sent: Tuesday, April 11, 2000 12:35 PM
> To: [email protected]
> Subject: [SI-LIST] : IBIS question regards [Falling Waveform] / [Rising
> Waveform].
>
>
> My question regards: [Falling Waveform] / [Rising Waveform].
>
> Our I/O buffer, output stage, contains the following structure:
> <<...>>
> while performing a rising transient on the pad , the ndrv signal
> "brakes"
> before the pdrv "mates".
> This cause a strange wave on the pad while simulating a [Rising
> Waveform]
> with R_fixture (resistor) connected to Vcc:
> The PAD begin to rise and even get to almost full swing before the Pmos
> opens.
> This cause a steepest slope of the [Rising Waveform] while simulating
> R_fixture connected to ground rather than R_fixture connected to Vcc .
>
> Waves forms:
> <<...>>
>
> Is this kind of wave is "harmful" to the IBIS model users? should I omit
> it,
> and leave only the [Rising Waveform] with resistor connected to ground ?
>
> Thanks,
> Merav.
>
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