From: Ron Miller ([email protected])
Date: Fri Apr 07 2000 - 15:34:41 PDT
A technique which though sub-optimal, helps is to run the traces through the
chip pads and continue on to an open area, terminating there. What happens
is you get a capacitve glitch on the TDR a few picoseconds before the term.
> -----Original Message-----
> From: [email protected]
> Sent: Friday, April 07, 2000 1:17 PM
> To: [email protected]
> Subject: [SI-LIST] : Terminator location with larger BGA's
> We are using some 484 pin BGA's (FPGA's), which have edge rates of about
> Using a series termination, it would have to be placed within 1/10 of the
> transition length according to Howard Johnson. On FR4, the transition
> would be .98, making the distance from source to termination .098. It is
> possible to get all of the required termination's within that distance.
> Aside from slowing down the edges (not desirable), waiting longer for
> things to
> settle, or going with buried resistance, are there any other solutions for
> placement of termination's? How are other people terminating large, high
> count devices?
> Bill McGiffin
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