RE: [SI-LIST] : PLL clock buffer chips and the feedback loop

About this list Date view Thread view Subject view Author view

From: Andy Peters ([email protected])
Date: Thu Apr 06 2000 - 14:58:35 PDT


> I've been following this thread off and on, mostly becasuse I'm involved
> doing the same exact type of design -- distributing clocks to an FPGA and
> banks of SRAM using RoboClock. If your clock driver is short of outputs,
> and your FPGA is from the Xilinx Virtex family, one option is to drive the
> SRAMS clocks from the FPGA using a DLL clock mirror. The technique is
> described in the Xilinx app notes. Depending on the number of outputs
> required, I've acheived 350ps of skew between the clock at the FPGA input
> and the clock(s) at the SRAMS.

Nope, it's a 4KXLA part. I didn't want to deal with a 2.5v power supply (in
addition to the 3.3V and the 5V). Another concern was that when I started
this project, there were still issues with the Xilinx tools and the Virtex

Had I started this project today, I would have used a Spartan2 part and a
different VME interface chip set. But, you know, you rolls your dice and
you moves your mice . . .


Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
520 318 8191
[email protected]

"Money is property; it is not speech."
            -- Justice John Paul Stevens

**** To unsubscribe from si-list or si-list-digest: send e-mail to [email protected] In the BODY of message put: UNSUBSCRIBE si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at

About this list Date view Thread view Subject view Author view

This archive was generated by hypermail 2b29 : Thu Apr 20 2000 - 11:36:05 PDT