RE: [SI-LIST] : PLL clock buffer chips and the feedback loop

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From: Ingraham, Andrew ([email protected])
Date: Thu Apr 06 2000 - 05:08:54 PDT

One thing not mentioned previously, is what else you will be doing with the
clock that goes into to the PLL.

Generally, people use a "zero delay" or PLL-based clock buffer when they
must control the delay THROUGH the clock buffer, that is, to control clock
skew between all your SDRAMs/FPGAs, and whatever other devices use the
upstream clock before the PLL.

If this delay is unimportant to you, then drop the PLL and use an ordinary
non-PLL clock buffer. The only purpose of the PLL is to control or null the
delay through the clock fanout part. It has no effect on skew between the
chip's outputs.

For example it looks here like you are driving the PLL input with an
oscillator. If that oscillator goes nowhere else, then you certainly don't
need a PLL in the clock buffer, and should eliminate it! The PLL adds
complexity and clock jitter, and you must use very good bypassing of the PLL
chip and isolate any loop filter pins, or it's going to have noisy outputs.

Also, cascading PLLs has risks. In extreme cases, the combination can be
unstable. More likely, it can in some cases make the downstream PLL's
outputs very jittery, with a lot of effective skew between the two PLLs. I
have heard of designs that were unusable because of cascaded PLLs.

You might already have two cascaded PLLs if the "oscillator" itself is
PLL-based. Cascading a third increases the risk.

Regarding the <1ms start-up time, are you sure that (a) the power supplies,
and (b) the oscillator, come up and into spec fast enough? Even XTAL
oscillators can take some time to start up and stabilize, and 1ms is not a
lot of time. ~50ms is not uncommon for just a PC supply to ramp up; much
more if multiple power rails are involved.


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