From: sweir ([email protected])
Date: Tue Apr 04 2000 - 20:33:02 PDT
If I understand correctly you are proposing two combs at 90 degrees to each
other, joined by a series of decoupling capacitors. If this is correct
then I recommend changes. This isn't quite as bad as the old parallel comb
designs, but it isn't that much better. The improvement is limited by the
mounted inductance of the decoupling capacitors at the intersections. You
will be better off using a gridding technique such as discussed a couple of
weeks ago by folks from Lexmark. That requires both voltages on both
planes, but with generally the same idea, N-S on one side of the board and
E-W on the other. You can find similar discussion in Dr. Johnson's book
"High Speed Digital Design".
The choice of capacitor values depends on what is happening on your
board. There has been a lot of discussion on this. The most vocal experts
appear to be the people from SUN, ( including the list moderator ) who have
done a lot of research on this subject.
Generally, the credible choices are either to "carpet bomb" with a single
type of capacitor or, to carefully choose capacitors in small value
increments. If you are just the poor layout guy, then stick with one value
such as .1 uF in the smallest, lowest inductance package that is practical,
and place as many as is practical. This is by no means the most
intelligent approach, but without EE support it is likely the best that you
can do. The problem with using decade spaced values is that the better the
capacitors are, the more likely that you will be adversely affected by the
antiresonance that occurs between the self-resonant frequencies of the
capacitors as they are mounted.
Larry Smith has presented on this topic, and discussed it on this thread
repeatedly in the recent past. The approach he describes has been used
very successfully and could potentially save your customer both money and
grief. The catch is that someone has to do their homework.
At 10:00 PM 4/4/00 -0400, you wrote:
>Hello SI experts,
>I'm relaying out a pcb for one of my customers. The goal is to reduce the cost
>by going from 4-layer (internal PWR and GND planes) bd. down to 2-layers. One
>of the major concerns is increased EMI.
>One of the ideas that was brought up to minimize EMI is to have a "grid" of
>horizontal PWR traces spaced around 2cm from each other on top side and
>vertical GND traces spaced 2cm on the opposite side. In addition, the board
>would have a GND ring around the perimeter on both sides that would be stiched
>with vias. Every point of intersection of these PWR and GND lines will have a
>.01uF and .1uF bypass cap.
>Since I haven't heard about this approach, your input would be appreciated.
>**** To unsubscribe from si-list or si-list-digest: send e-mail to
>[email protected] In the BODY of message put: UNSUBSCRIBE
>si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
>si-list archives are accessible at http://www.qsl.net/wb6tpu
**** To unsubscribe from si-list or si-list-digest: send e-mail to [email protected] In the BODY of message put: UNSUBSCRIBE si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu
This archive was generated by hypermail 2b29 : Thu Apr 20 2000 - 11:36:02 PDT