[SI-LIST] : PLL clock buffer chips and the feedback loop

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From: Andy Peters ([email protected])
Date: Mon Apr 03 2000 - 11:06:06 PDT

When using "zero-skew" PLL clock buffer chips (such as the Cypress
RoboClock), where do you bring the feedback from? Cypress' data sheets and
app notes are notoriously (and typically, I might add) unclear on this -
they simply indicate that it comes from "one of the outputs."

For instance, my board has an FPGA that talks to four SDRAM devices. It
seems to me that one buffer output could drive the FPGA's clock pin (via
series termination) and four of the other outputs could drive the four SDRAM
clocks (again, through series terminations). Assume that my clock line
lengths are equal, to minimize board skew. Do I take the feedback from one
of the destination pins, and match the line length? Or is it sufficient to
simply connect one of the outputs to the feedback pin right at the chip?

Are there any other vendors of these sorts of devices? Spread-spectrum
capability is not required.



ps: I sent a short e-mail to the sales-droids at Accel, asking some simple
questions about their signal integrity tool. Since they were apparently too
busy to bother replying, I am no longer considering their product.

Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
520 318 8191
[email protected]

"Money is property; it is not speech."
            -- Justice John Paul Stevens

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